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AIA: Add APLIC support
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9 files changed

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9 files changed

+398
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‎riscv/aplic.cc

Lines changed: 295 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,295 @@
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// See LICENSE for license details.
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#include "devices.h"
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#include "processor.h"
4+
#include "arith.h"
5+
#include "sim.h"
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7+
#define DOMAINCFG 0x0
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#define SOURCECFG_BASE 0x4
9+
#define MMSIADDRCFG 0x1bc0
10+
#define MMSIADDRCFGH 0x1bc4
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#define SMSIADDRCFG 0x1bc8
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#define SMSIADDRCFGH 0x1bcc
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#define SETIP_BASE 0x1c00
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#define SETIPNUM 0x1cdc
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#define IN_CLRIP_BASE 0x1d00
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#define CLRIPNUM 0x1ddc
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#define SETIE_BASE 0x1e00
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#define SETIENUM 0x1edc
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#define CLRIE_BASE 0x1f00
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#define CLRIENUM 0x1fdc
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#define GENMSI 0x3000
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#define TARGET_BASE 0x3004
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#define IDC 0x4000
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#define DOMAINCFG_IE_MASK 0x100
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#define DOMAINCFG_DM_MASK 0x4
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#define SOURCECFG_D_MASK 0x400
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#define SOURCECFG_CHILD_MASK 0x3ff
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#define SOURCECFG_SM_MASK 0x7
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32+
#define MMSIADDRCFGH_L_MASK 0x80000000
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#define GENMSI_HART_MASK 0xfffc0000
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#define GENMSI_BUSY_MASK 0x1000
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#define GENMSI_EIID_MASK 0x7ff
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#define TARGET_HART_MASK 0xfffc0000
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#define TARGET_GUEST_MASK 0x3f000
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#define TARGET_EIID_MASK 0x7ff
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aplic_t::aplic_t(std::vector<processor_t*>& procs, aplic_t *parent) : procs(procs), parent(parent), child(nullptr), domaincfg((0x80 << 24) | DOMAINCFG_DM_MASK), sourcecfg(), mmsiaddrcfgh(MMSIADDRCFGH_L_MASK), ie(), target(), level(), genmsi(0), deleg_mask()
43+
{
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}
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void aplic_t::delegate(uint32_t id, bool dm)
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{
48+
if (!id || id >= APLIC_MAX_DEVICES)
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return;
50+
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if (!child) {
52+
// child's sourcecfg = 0 when interrupt is changed to delegated
53+
if (!parent->delegated(id) && dm)
54+
sourcecfg[id] = 0;
55+
} else {
56+
uint32_t mask = (1 << (id % 32));
57+
deleg_mask[id / 32] &= ~mask;
58+
deleg_mask[id / 32] |= dm ? mask : 0;
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child->delegate(id, dm);
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}
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}
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bool aplic_t::delegated(uint32_t id)
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{
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if (!id || id >= APLIC_MAX_DEVICES)
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return false;
67+
return (sourcecfg[id] & SOURCECFG_D_MASK);
68+
}
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uint32_t aplic_t::get_deleg_mask(uint32_t idx) {
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if (idx >= APLIC_MAX_DEVICES / 32)
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return 0;
73+
if (parent)
74+
return parent->get_deleg_mask(idx);
75+
return deleg_mask[idx];
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}
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bool aplic_t::interrupt_enabled(uint32_t id)
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{
80+
if (!id || id >= APLIC_MAX_DEVICES)
81+
return false;
82+
if (parent && !parent->delegated(id))
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return false;
84+
// Domain interrupt enabled, source IE and source mode != inactive (0)
85+
return (domaincfg & DOMAINCFG_IE_MASK) && (ie[id / 32] & (1 << (id % 32))) && (sourcecfg[id] & SOURCECFG_SM_MASK);
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}
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bool aplic_t::accessible(uint32_t id)
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{
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if (!id || id >= APLIC_MAX_DEVICES)
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return false;
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if (!parent)
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return true;
94+
return parent->delegated(id);
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}
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void aplic_t::set_interrupt_level(uint32_t id, int lvl)
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{
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if (child && delegated(id)) {
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child->set_interrupt_level(id, lvl);
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return;
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}
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if (!accessible(id))
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return;
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uint32_t mask = 1 << (id % 32);
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level[id / 32] &= ~mask;
109+
level[id / 32] |= lvl ? mask : 0;
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update_interrupt(id);
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}
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void aplic_t::send_msi(uint32_t proc_id, uint32_t guest, uint32_t eiid)
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{
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if (!eiid || proc_id >= procs.size())
117+
return;
118+
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auto proc = procs[proc_id];
120+
if (!parent) {
121+
proc->imsic->m->pendei(eiid);
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} else if (guest) {
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if (proc->imsic->vs.count(guest))
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proc->imsic->vs[guest]->pendei(eiid);
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} else {
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proc->imsic->s->pendei(eiid);
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}
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}
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void aplic_t::send_msi(uint32_t id)
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{
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if (id >= APLIC_MAX_DEVICES)
133+
return;
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auto tgt = target[id];
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send_msi(get_field(tgt, TARGET_HART_MASK), get_field(tgt, TARGET_GUEST_MASK), get_field(tgt, TARGET_EIID_MASK));
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}
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void aplic_t::update_interrupt(uint32_t id)
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{
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// check level and if interrupt enabled, send MSI if necessary
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if (id >= APLIC_MAX_DEVICES)
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return;
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bool lvl = level[id / 32] & (1 << (id % 32));
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if (lvl && interrupt_enabled(id))
145+
send_msi(id);
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}
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void aplic_t::update_interrupt_masked(uint32_t idx, uint32_t mask)
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{
150+
if (idx >= APLIC_MAX_DEVICES / 32)
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return;
152+
while(mask) {
153+
auto id = ctz(mask);
154+
update_interrupt(idx * 32 + id);
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mask &= ~(1 << id);
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}
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}
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bool aplic_t::load(reg_t addr, size_t len, uint8_t* bytes)
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{
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uint32_t val = 0;
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if (len != 4) {
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return false;
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}
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addr &= ~reg_t(3);
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if (addr == DOMAINCFG) {
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val = domaincfg;
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} else if (addr >= SOURCECFG_BASE && addr < MMSIADDRCFG) {
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auto idx = (addr - SOURCECFG_BASE) / 4 + 1;
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if (accessible(idx))
174+
val = sourcecfg[idx];
175+
} else if (addr == MMSIADDRCFGH) {
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val = mmsiaddrcfgh;
177+
} else if (addr >= IN_CLRIP_BASE && addr < CLRIPNUM) {
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auto idx = (addr - IN_CLRIP_BASE) / 4;
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val = level[idx];
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} else if (addr >= SETIE_BASE && addr < SETIENUM) {
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auto idx = (addr - SETIE_BASE) / 4;
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val = ie[idx];
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} else if (addr == GENMSI) {
184+
val = genmsi;
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} else if (addr >= TARGET_BASE && addr < IDC) {
186+
auto idx = (addr - TARGET_BASE) / 4 + 1;
187+
if (accessible(idx))
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val = target[idx];
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}
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memcpy(bytes, (uint8_t *)&val, len);
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return true;
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}
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bool aplic_t::store(reg_t addr, size_t len, const uint8_t* bytes)
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{
198+
uint32_t val = 0;
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if (len != 4) {
201+
return false;
202+
}
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addr &= ~reg_t(3);
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memcpy((uint8_t *)&val, bytes, len);
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if (addr == DOMAINCFG) {
208+
domaincfg &= ~DOMAINCFG_IE_MASK;
209+
domaincfg |= val & DOMAINCFG_IE_MASK;
210+
} else if (addr >= SOURCECFG_BASE && addr < MMSIADDRCFG) {
211+
auto idx = (addr - SOURCECFG_BASE) / 4 + 1;
212+
// write to D bit sets child's sourcecfg to 0
213+
// SM = inactive (0) or Level1 (6)
214+
if (accessible(idx)) {
215+
if (!child && (val & SOURCECFG_D_MASK))
216+
val = 0;
217+
else if (child)
218+
delegate(idx, val & SOURCECFG_D_MASK);
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// force SM to be 6 if non-zero
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if (val & SOURCECFG_SM_MASK)
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val = set_field(val, SOURCECFG_SM_MASK, 6);
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sourcecfg[idx] = val;
225+
}
226+
} else if (addr >= SETIP_BASE && addr < SETIPNUM) {
227+
auto idx = (addr - SETIP_BASE) / 4;
228+
val &= get_deleg_mask(idx);
229+
update_interrupt_masked(idx, val);
230+
} else if (addr == SETIPNUM) {
231+
update_interrupt(val);
232+
} else if (addr >= SETIE_BASE && addr < SETIENUM) {
233+
auto idx = (addr - SETIE_BASE) / 4;
234+
val &= get_deleg_mask(idx);
235+
ie[idx] |= val;
236+
} else if (addr == SETIENUM) {
237+
if (accessible(val))
238+
ie[val / 32] |= 1 << (val % 32);
239+
} else if (addr >= CLRIE_BASE && addr < CLRIENUM) {
240+
auto idx = (addr - CLRIE_BASE) / 4;
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val &= get_deleg_mask(idx);
242+
ie[idx] &= ~val;
243+
} else if (addr == CLRIENUM) {
244+
if (accessible(val))
245+
ie[val / 32] &= ~(1 << (val % 32));
246+
} else if (addr == GENMSI) {
247+
genmsi = val & (GENMSI_HART_MASK | GENMSI_EIID_MASK);
248+
send_msi(get_field(genmsi, GENMSI_HART_MASK), 0, get_field(genmsi, GENMSI_EIID_MASK));
249+
} else if (addr >= TARGET_BASE && addr < IDC) {
250+
auto idx = (addr - TARGET_BASE) / 4 + 1;
251+
if (accessible(val))
252+
target[idx] = val;
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}
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return true;
256+
}
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std::string aplic_generate_dts(const sim_t* sim, const std::vector<std::string>& sargs UNUSED)
259+
{
260+
auto cfg = sim->get_cfg();
261+
isa_parser_t isa(cfg.isa, cfg.priv);
262+
std::stringstream s;
263+
if (isa.extension_enabled(EXT_SMAIA)) {
264+
s << std::hex
265+
<< " APLIC_M: aplic@" << APLIC_M_BASE << " {\n"
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" riscv,delegate = <&APLIC_S 0x01 0x35>;\n"
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" riscv,children = <&APLIC_S>;\n"
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" riscv,num-sources = <0x35>;\n"
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" reg = <0x00 0x" << APLIC_M_BASE << " 0x00 0x" << APLIC_SIZE << ">;\n"
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" msi-parent = <&IMSIC_M>;\n"
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" interrupt-controller;\n"
272+
" #interrupt-cells = <0x02>;\n"
273+
" compatible = \"riscv,aplic\";\n"
274+
" };\n";
275+
}
276+
if (isa.extension_enabled(EXT_SSAIA)) {
277+
s << std::hex
278+
<< " APLIC_S: aplic@" << APLIC_S_BASE << " {\n"
279+
" riscv,num-sources = <0x35>;\n"
280+
" reg = <0x00 0x" << APLIC_S_BASE << " 0x00 0x" << APLIC_SIZE << ">;\n"
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" msi-parent = <&IMSIC_S>;\n"
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" interrupt-controller;\n"
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" #interrupt-cells = <0x02>;\n"
284+
" compatible = \"riscv,aplic\";\n"
285+
" };\n";
286+
}
287+
return s.str();
288+
}
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aplic_t* aplic_parse_from_fdt(const void* fdt, const sim_t* sim, reg_t* base, const std::vector<std::string>& sargs UNUSED)
291+
{
292+
return nullptr;
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}
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REGISTER_DEVICE(aplic, aplic_parse_from_fdt, aplic_generate_dts)

‎riscv/devices.h

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -159,6 +159,40 @@ class plic_t : public abstract_device_t, public abstract_interrupt_controller_t
159159
reg_t offset, uint32_t val);
160160
};
161161

162+
#define APLIC_MAX_DEVICES 1024
163+
class aplic_t : public abstract_device_t, public abstract_interrupt_controller_t {
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public:
165+
aplic_t(std::vector<processor_t*>&, aplic_t *parent);
166+
bool load(reg_t addr, size_t len, uint8_t* bytes);
167+
bool store(reg_t addr, size_t len, const uint8_t* bytes);
168+
void set_interrupt_level(uint32_t id, int lvl);
169+
size_t size() { return APLIC_SIZE; }
170+
void set_child(aplic_t *c) { child = c; }
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void delegate(uint32_t id, bool dm);
172+
bool delegated(uint32_t id);
173+
uint32_t get_deleg_mask(uint32_t idx);
174+
private:
175+
std::vector<processor_t*>& procs;
176+
class aplic_t *parent;
177+
class aplic_t *child;
178+
uint32_t domaincfg;
179+
uint32_t sourcecfg[APLIC_MAX_DEVICES];
180+
uint32_t mmsiaddrcfgh;
181+
uint32_t ie[APLIC_MAX_DEVICES / 32];
182+
uint32_t target[APLIC_MAX_DEVICES];
183+
uint32_t level[APLIC_MAX_DEVICES / 32];
184+
uint32_t genmsi;
185+
// deleg_mask can be directly applied to other packed registers
186+
uint32_t deleg_mask[APLIC_MAX_DEVICES / 32];
187+
188+
bool interrupt_enabled(uint32_t id);
189+
bool accessible(uint32_t id);
190+
void send_msi(uint32_t proc_id, uint32_t guest, uint32_t eiid);
191+
void send_msi(uint32_t id);
192+
void update_interrupt(uint32_t id);
193+
void update_interrupt_masked(uint32_t idx, uint32_t mask);
194+
};
195+
162196
class ns16550_t : public abstract_device_t {
163197
public:
164198
ns16550_t(abstract_interrupt_controller_t *intctrl,

‎riscv/dts.cc

Lines changed: 27 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -446,14 +446,14 @@ int fdt_parse_imsics(const void *fdt, reg_t *imsic_m_addr, reg_t *imsic_s_addr,
446446
{
447447
int nodeoffset = -1, len, rc;
448448
const fdt32_t *p;
449-
reg_t addr = 0;
450449
int val;
451450

452451
for (int i = 0; i < 2; i++) {
453452
nodeoffset = fdt_node_offset_by_compatible(fdt, nodeoffset, compatible);
454453
if (nodeoffset < 0)
455454
return nodeoffset;
456455

456+
reg_t addr = 0;
457457
rc = fdt_get_node_addr_size(fdt, nodeoffset, &addr, NULL, "reg");
458458
if (rc < 0)
459459
return -ENODEV;
@@ -470,3 +470,29 @@ int fdt_parse_imsics(const void *fdt, reg_t *imsic_m_addr, reg_t *imsic_s_addr,
470470
}
471471
return 0;
472472
}
473+
474+
int fdt_parse_aplic(const void *fdt, reg_t *aplic_m_addr, reg_t *aplic_s_addr, const char *compatible)
475+
{
476+
int nodeoffset = -1, len, rc;
477+
const fdt32_t *p;
478+
479+
for (int i = 0; i < 2; i++) {
480+
nodeoffset = fdt_node_offset_by_compatible(fdt, nodeoffset, compatible);
481+
if (nodeoffset < 0)
482+
return nodeoffset;
483+
484+
reg_t addr = 0;
485+
rc = fdt_get_node_addr_size(fdt, nodeoffset, &addr, NULL, "reg");
486+
if (rc < 0)
487+
return -ENODEV;
488+
489+
p = (fdt32_t *)fdt_getprop(fdt, nodeoffset, "riscv,children", &len);
490+
491+
if (p && aplic_m_addr)
492+
*aplic_m_addr = addr;
493+
else if (!p && aplic_s_addr)
494+
*aplic_s_addr = addr;
495+
}
496+
497+
return 0;
498+
}

‎riscv/dts.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -33,4 +33,5 @@ int fdt_parse_mmu_type(const void *fdt, int cpu_offset, const char **mmu_type);
3333
int fdt_parse_isa(const void *fdt, int cpu_offset, const char **isa_str);
3434
int fdt_parse_hartid(const void *fdt, int cpu_offset, uint32_t *hartid);
3535
int fdt_parse_imsics(const void *fdt, reg_t *imsic_m_addr, reg_t *imsic_s_addr, const char *compatible);
36+
int fdt_parse_aplic(const void *fdt, reg_t *aplic_m_addr, reg_t *aplic_s_addr, const char *compatible);
3637
#endif

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