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YenHaoChenYenHaoChen
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Merge pull request #1793 from rtwfroody/native_triggers2
Only implement one solution for native triggers.
2 parents cb78f09 + 0703b44 commit d7ded0c

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5 files changed

+53
-26
lines changed

5 files changed

+53
-26
lines changed

‎riscv/csr_init.cc

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -205,13 +205,14 @@ void state_t::csr_init(processor_t* const proc, reg_t max_isa)
205205
add_csr(CSR_TDATA2, tdata2 = std::make_shared<tdata2_csr_t>(proc, CSR_TDATA2));
206206
add_csr(CSR_TDATA3, std::make_shared<tdata3_csr_t>(proc, CSR_TDATA3));
207207
add_csr(CSR_TINFO, std::make_shared<tinfo_csr_t>(proc, CSR_TINFO));
208-
add_csr(CSR_TCONTROL, tcontrol = std::make_shared<masked_csr_t>(proc, CSR_TCONTROL, CSR_TCONTROL_MPTE | CSR_TCONTROL_MTE, 0));
208+
if (!proc->extension_enabled_const('S')) {
209+
add_csr(CSR_TCONTROL, tcontrol = std::make_shared<masked_csr_t>(proc, CSR_TCONTROL, CSR_TCONTROL_MPTE | CSR_TCONTROL_MTE, 0));
210+
}
209211
} else {
210212
add_csr(CSR_TDATA1, std::make_shared<const_csr_t>(proc, CSR_TDATA1, 0));
211213
add_csr(CSR_TDATA2, tdata2 = std::make_shared<const_csr_t>(proc, CSR_TDATA2, 0));
212214
add_csr(CSR_TDATA3, std::make_shared<const_csr_t>(proc, CSR_TDATA3, 0));
213215
add_csr(CSR_TINFO, std::make_shared<const_csr_t>(proc, CSR_TINFO, 0));
214-
add_csr(CSR_TCONTROL, tcontrol = std::make_shared<const_csr_t>(proc, CSR_TCONTROL, 0));
215216
}
216217
unsigned scontext_length = (xlen == 32 ? 16 : 32); // debug spec suggests 16-bit for RV32 and 32-bit for RV64
217218
add_supervisor_csr(CSR_SCONTEXT, scontext = std::make_shared<masked_csr_t>(proc, CSR_SCONTEXT, (reg_t(1) << scontext_length) - 1, 0));

‎riscv/insns/mret.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,5 +20,5 @@ if (prev_virt && prev_prv == PRV_U)
2020
STATE.vsstatus->write(STATE.vsstatus->read() & ~SSTATUS_SDT);
2121
STATE.mstatus->write(s);
2222
if (STATE.mstatush) STATE.mstatush->write(s >> 32); // log mstatush change
23-
STATE.tcontrol->write((STATE.tcontrol->read() & CSR_TCONTROL_MPTE) ? (CSR_TCONTROL_MPTE | CSR_TCONTROL_MTE) : 0);
23+
if (STATE.tcontrol) STATE.tcontrol->write((STATE.tcontrol->read() & CSR_TCONTROL_MPTE) ? (CSR_TCONTROL_MPTE | CSR_TCONTROL_MTE) : 0);
2424
p->set_privilege(prev_prv, prev_virt);

‎riscv/processor.cc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -535,7 +535,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
535535
state.elp = elp_t::NO_LP_EXPECTED;
536536
state.mstatus->write(s);
537537
if (state.mstatush) state.mstatush->write(s >> 32); // log mstatush change
538-
state.tcontrol->write((state.tcontrol->read() & CSR_TCONTROL_MTE) ? CSR_TCONTROL_MPTE : 0);
538+
if (state.tcontrol) state.tcontrol->write((state.tcontrol->read() & CSR_TCONTROL_MTE) ? CSR_TCONTROL_MPTE : 0);
539539
set_privilege(PRV_M, false);
540540
}
541541
}

‎riscv/triggers.cc

Lines changed: 48 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -55,12 +55,54 @@ void trigger_t::tdata3_write(processor_t * const proc, const reg_t val) noexcept
5555
sselect = (sselect_t)((proc->extension_enabled_const('S') && get_field(val, CSR_TEXTRA_SSELECT(xlen)) <= SSELECT_MAXVAL) ? get_field(val, CSR_TEXTRA_SSELECT(xlen)) : SSELECT_IGNORE);
5656
}
5757

58+
static reg_t tcontrol_value(const state_t * state) {
59+
if (state->tcontrol)
60+
return state->tcontrol->read();
61+
else
62+
return 0;
63+
}
64+
5865
bool trigger_t::common_match(processor_t * const proc, bool use_prev_prv) const noexcept {
5966
auto state = proc->get_state();
6067
auto prv = use_prev_prv ? state->prev_prv : state->prv;
6168
auto v = use_prev_prv ? state->prev_v : state->v;
62-
auto m_enabled = get_action() != 0 || (state->tcontrol->read() & CSR_TCONTROL_MTE);
63-
return (prv < PRV_M || m_enabled) && mode_match(prv, v) && textra_match(proc);
69+
70+
if (!mode_match(prv, v))
71+
return false;
72+
73+
if (!textra_match(proc))
74+
return false;
75+
76+
if (get_action() == ACTION_DEBUG_EXCEPTION) {
77+
if (proc->extension_enabled('S')) {
78+
// The hardware prevents triggers with action=0 from matching or firing
79+
// while in M-mode and while MIE in mstatus is 0. If medeleg [3]=1 then it
80+
// prevents triggers with action=0 from matching or firing while in S-mode
81+
// and while SIE in sstatus is 0. If medeleg [3]=1 and hedeleg [3]=1 then
82+
// it prevents triggers with action=0 from matching or firing while in
83+
// VS-mode and while SIE in vstatus is 0.
84+
85+
const bool mstatus_mie = state->mstatus->read() & MSTATUS_MIE;
86+
if (prv == PRV_M && !mstatus_mie)
87+
return false;
88+
89+
const bool sstatus_sie = state->sstatus->read() & MSTATUS_SIE;
90+
const bool medeleg_breakpoint = (state->medeleg->read() >> CAUSE_BREAKPOINT) & 1;
91+
if (prv == PRV_S && !v && medeleg_breakpoint && !sstatus_sie)
92+
return false;
93+
94+
const bool vsstatus_sie = state->vsstatus->read() & MSTATUS_SIE;
95+
const bool hedeleg_breakpoint = (state->hedeleg->read() >> CAUSE_BREAKPOINT) & 1;
96+
if (prv == PRV_S && v && medeleg_breakpoint && hedeleg_breakpoint && !vsstatus_sie)
97+
return false;
98+
} else {
99+
// mte and mpte in tcontrol is implemented. medeleg [3] is hard-wired to 0.
100+
if (prv == PRV_M && !(tcontrol_value(state) & CSR_TCONTROL_MTE))
101+
return false;
102+
}
103+
}
104+
105+
return true;
64106
}
65107

66108
bool trigger_t::mode_match(reg_t prv, bool v) const noexcept
@@ -110,21 +152,6 @@ bool trigger_t::textra_match(processor_t * const proc) const noexcept
110152
return true;
111153
}
112154

113-
bool trigger_t::allow_action(const state_t * const state) const
114-
{
115-
if (get_action() == ACTION_DEBUG_EXCEPTION) {
116-
const bool mstatus_mie = state->mstatus->read() & MSTATUS_MIE;
117-
const bool sstatus_sie = state->sstatus->read() & MSTATUS_SIE;
118-
const bool vsstatus_sie = state->vsstatus->read() & MSTATUS_SIE;
119-
const bool medeleg_breakpoint = (state->medeleg->read() >> CAUSE_BREAKPOINT) & 1;
120-
const bool hedeleg_breakpoint = (state->hedeleg->read() >> CAUSE_BREAKPOINT) & 1;
121-
return (state->prv != PRV_M || mstatus_mie) &&
122-
(state->prv != PRV_S || state->v || !medeleg_breakpoint || sstatus_sie) &&
123-
(state->prv != PRV_S || !state->v || !medeleg_breakpoint || !hedeleg_breakpoint || vsstatus_sie);
124-
}
125-
return true;
126-
}
127-
128155
reg_t disabled_trigger_t::tdata1_read(const processor_t * const proc) const noexcept
129156
{
130157
auto xlen = proc->get_xlen();
@@ -235,7 +262,7 @@ std::optional<match_result_t> mcontrol_common_t::detect_memory_access_match(proc
235262
value &= 0xffffffff;
236263
}
237264

238-
if (simple_match(xlen, value) && allow_action(proc->get_state())) {
265+
if (simple_match(xlen, value)) {
239266
/* This is OK because this function is only called if the trigger was not
240267
* inhibited by the previous trigger in the chain. */
241268
set_hit(timing ? HIT_IMMEDIATELY_AFTER : HIT_BEFORE);
@@ -324,7 +351,7 @@ void mcontrol6_t::tdata1_write(processor_t * const proc, const reg_t val, const
324351

325352
std::optional<match_result_t> icount_t::detect_icount_fire(processor_t * const proc) noexcept
326353
{
327-
if (!common_match(proc) || !allow_action(proc->get_state()))
354+
if (!common_match(proc))
328355
return std::nullopt;
329356

330357
std::optional<match_result_t> ret = std::nullopt;
@@ -339,7 +366,7 @@ std::optional<match_result_t> icount_t::detect_icount_fire(processor_t * const p
339366

340367
void icount_t::detect_icount_decrement(processor_t * const proc) noexcept
341368
{
342-
if (!common_match(proc) || !allow_action(proc->get_state()))
369+
if (!common_match(proc))
343370
return;
344371

345372
if (count >= 1) {
@@ -431,7 +458,7 @@ std::optional<match_result_t> trap_common_t::detect_trap_match(processor_t * con
431458
bool interrupt = (t.cause() & ((reg_t)1 << (xlen - 1))) != 0;
432459
reg_t bit = t.cause() & ~((reg_t)1 << (xlen - 1));
433460
assert(bit < xlen);
434-
if (simple_match(interrupt, bit) && allow_action(proc->get_state())) {
461+
if (simple_match(interrupt, bit)) {
435462
hit = true;
436463
return match_result_t(TIMING_AFTER, action);
437464
}

‎riscv/triggers.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -99,7 +99,6 @@ class trigger_t {
9999
protected:
100100
static action_t legalize_action(reg_t val, reg_t action_mask, reg_t dmode_mask) noexcept;
101101
bool common_match(processor_t * const proc, bool use_prev_prv = false) const noexcept;
102-
bool allow_action(const state_t * const state) const;
103102
reg_t tdata2;
104103

105104
bool vs = false;

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