Skip to content

Commit cb78f09

Browse files
aswatermanaswaterman
authored
Merge pull request #1797 from YenHaoChen/pr-vector
vector: disassemble: Let operand ordering be vd, [vrf]s1, vs2 to vector multiply-add instructions
2 parents 2538c1f + 6a1a5db commit cb78f09

File tree

1 file changed

+48
-20
lines changed

1 file changed

+48
-20
lines changed

‎disasm/disasm.cc

Lines changed: 48 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -735,16 +735,31 @@ static void NOINLINE add_vector_vv_insn(disassembler_t* d, const char* name, uin
735735
d->add_insn(new disasm_insn_t(name, match, mask, {&vd, &vs2, &vs1, opt, &vm}));
736736
}
737737

738+
static void NOINLINE add_vector_multiplyadd_vv_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask)
739+
{
740+
d->add_insn(new disasm_insn_t(name, match, mask, {&vd, &vs1, &vs2, opt, &vm}));
741+
}
742+
738743
static void NOINLINE add_vector_vx_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask)
739744
{
740745
d->add_insn(new disasm_insn_t(name, match, mask, {&vd, &vs2, &xrs1, opt, &vm}));
741746
}
742747

748+
static void NOINLINE add_vector_multiplyadd_vx_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask)
749+
{
750+
d->add_insn(new disasm_insn_t(name, match, mask, {&vd, &xrs1, &vs2, opt, &vm}));
751+
}
752+
743753
static void NOINLINE add_vector_vf_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask)
744754
{
745755
d->add_insn(new disasm_insn_t(name, match, mask, {&vd, &vs2, &frs1, opt, &vm}));
746756
}
747757

758+
static void NOINLINE add_vector_multiplyadd_vf_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask)
759+
{
760+
d->add_insn(new disasm_insn_t(name, match, mask, {&vd, &frs1, &vs2, opt, &vm}));
761+
}
762+
748763
static void NOINLINE add_vector_vi_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask)
749764
{
750765
d->add_insn(new disasm_insn_t(name, match, mask, {&vd, &vs2, &v_simm5, opt, &vm}));
@@ -1642,8 +1657,11 @@ void disassembler_t::add_instructions(const isa_parser_t* isa)
16421657

16431658
#define DEFINE_VECTOR_V(code) add_vector_v_insn(this, #code, match_##code, mask_##code)
16441659
#define DEFINE_VECTOR_VV(code) add_vector_vv_insn(this, #code, match_##code, mask_##code)
1660+
#define DEFINE_VECTOR_MULTIPLYADD_VV(code) add_vector_multiplyadd_vv_insn(this, #code, match_##code, mask_##code)
16451661
#define DEFINE_VECTOR_VX(code) add_vector_vx_insn(this, #code, match_##code, mask_##code)
1662+
#define DEFINE_VECTOR_MULTIPLYADD_VX(code) add_vector_multiplyadd_vx_insn(this, #code, match_##code, mask_##code)
16461663
#define DEFINE_VECTOR_VF(code) add_vector_vf_insn(this, #code, match_##code, mask_##code)
1664+
#define DEFINE_VECTOR_MULTIPLYADD_VF(code) add_vector_multiplyadd_vf_insn(this, #code, match_##code, mask_##code)
16471665
#define DEFINE_VECTOR_VI(code) add_vector_vi_insn(this, #code, match_##code, mask_##code)
16481666
#define DEFINE_VECTOR_VIU(code) add_vector_viu_insn(this, #code, match_##code, mask_##code)
16491667

@@ -1659,6 +1677,10 @@ void disassembler_t::add_instructions(const isa_parser_t* isa)
16591677
DEFINE_VECTOR_VV(name##_vv); \
16601678
DEFINE_VECTOR_VX(name##_vx)
16611679

1680+
#define DISASM_OPIV_MULTIPLYADD_VX__INSN(name, sign) \
1681+
DEFINE_VECTOR_MULTIPLYADD_VV(name##_vv); \
1682+
DEFINE_VECTOR_MULTIPLYADD_VX(name##_vx)
1683+
16621684
#define DISASM_OPIV__XI_INSN(name, sign) \
16631685
DEFINE_VECTOR_VX(name##_vx); \
16641686
if (sign) \
@@ -1678,6 +1700,8 @@ void disassembler_t::add_instructions(const isa_parser_t* isa)
16781700

16791701
#define DISASM_OPIV__X__INSN(name, sign) DEFINE_VECTOR_VX(name##_vx)
16801702

1703+
#define DISASM_OPIV_MULTIPLYADD__X__INSN(name, sign) DEFINE_VECTOR_MULTIPLYADD_VX(name##_vx)
1704+
16811705
#define DEFINE_VECTOR_VVM(name) \
16821706
add_vector_vvm_insn(this, #name, match_##name, mask_##name | mask_vm)
16831707

@@ -1821,10 +1845,10 @@ void disassembler_t::add_instructions(const isa_parser_t* isa)
18211845
DISASM_OPIV_VX__INSN(vmul, 1);
18221846
DISASM_OPIV_VX__INSN(vmulhsu, 0);
18231847
DISASM_OPIV_VX__INSN(vmulh, 1);
1824-
DISASM_OPIV_VX__INSN(vmadd, 1);
1825-
DISASM_OPIV_VX__INSN(vnmsub, 1);
1826-
DISASM_OPIV_VX__INSN(vmacc, 1);
1827-
DISASM_OPIV_VX__INSN(vnmsac, 1);
1848+
DISASM_OPIV_MULTIPLYADD_VX__INSN(vmadd, 1);
1849+
DISASM_OPIV_MULTIPLYADD_VX__INSN(vnmsub, 1);
1850+
DISASM_OPIV_MULTIPLYADD_VX__INSN(vmacc, 1);
1851+
DISASM_OPIV_MULTIPLYADD_VX__INSN(vnmsac, 1);
18281852

18291853
//0b11_0000
18301854
DISASM_OPIV_VX__INSN(vwaddu, 0);
@@ -1838,10 +1862,10 @@ void disassembler_t::add_instructions(const isa_parser_t* isa)
18381862
DISASM_OPIV_VX__INSN(vwmulu, 0);
18391863
DISASM_OPIV_VX__INSN(vwmulsu, 0);
18401864
DISASM_OPIV_VX__INSN(vwmul, 1);
1841-
DISASM_OPIV_VX__INSN(vwmaccu, 0);
1842-
DISASM_OPIV_VX__INSN(vwmacc, 1);
1843-
DISASM_OPIV__X__INSN(vwmaccus, 1);
1844-
DISASM_OPIV_VX__INSN(vwmaccsu, 0);
1865+
DISASM_OPIV_MULTIPLYADD_VX__INSN(vwmaccu, 0);
1866+
DISASM_OPIV_MULTIPLYADD_VX__INSN(vwmacc, 1);
1867+
DISASM_OPIV_MULTIPLYADD__X__INSN(vwmaccus, 1);
1868+
DISASM_OPIV_MULTIPLYADD_VX__INSN(vwmaccsu, 0);
18451869

18461870
#undef DISASM_OPIV_VXI_INSN
18471871
#undef DISASM_OPIV_VX__INSN
@@ -1858,6 +1882,10 @@ void disassembler_t::add_instructions(const isa_parser_t* isa)
18581882
DEFINE_VECTOR_VV(name##_vv); \
18591883
DEFINE_VECTOR_VF(name##_vf)
18601884

1885+
#define DISASM_OPIV_MULTIPLYADD_VF_INSN(name) \
1886+
DEFINE_VECTOR_MULTIPLYADD_VV(name##_vv); \
1887+
DEFINE_VECTOR_MULTIPLYADD_VF(name##_vf)
1888+
18611889
#define DISASM_OPIV_WF_INSN(name) \
18621890
DEFINE_VECTOR_VV(name##_wv); \
18631891
DEFINE_VECTOR_VF(name##_wf)
@@ -1925,14 +1953,14 @@ void disassembler_t::add_instructions(const isa_parser_t* isa)
19251953

19261954
DISASM_OPIV_VF_INSN(vfmul);
19271955
DISASM_OPIV__F_INSN(vfrsub);
1928-
DISASM_OPIV_VF_INSN(vfmadd);
1929-
DISASM_OPIV_VF_INSN(vfnmadd);
1930-
DISASM_OPIV_VF_INSN(vfmsub);
1931-
DISASM_OPIV_VF_INSN(vfnmsub);
1932-
DISASM_OPIV_VF_INSN(vfmacc);
1933-
DISASM_OPIV_VF_INSN(vfnmacc);
1934-
DISASM_OPIV_VF_INSN(vfmsac);
1935-
DISASM_OPIV_VF_INSN(vfnmsac);
1956+
DISASM_OPIV_MULTIPLYADD_VF_INSN(vfmadd);
1957+
DISASM_OPIV_MULTIPLYADD_VF_INSN(vfnmadd);
1958+
DISASM_OPIV_MULTIPLYADD_VF_INSN(vfmsub);
1959+
DISASM_OPIV_MULTIPLYADD_VF_INSN(vfnmsub);
1960+
DISASM_OPIV_MULTIPLYADD_VF_INSN(vfmacc);
1961+
DISASM_OPIV_MULTIPLYADD_VF_INSN(vfnmacc);
1962+
DISASM_OPIV_MULTIPLYADD_VF_INSN(vfmsac);
1963+
DISASM_OPIV_MULTIPLYADD_VF_INSN(vfnmsac);
19361964

19371965
//0b11_0000
19381966
DISASM_OPIV_VF_INSN(vfwadd);
@@ -1942,10 +1970,10 @@ void disassembler_t::add_instructions(const isa_parser_t* isa)
19421970
DISASM_OPIV_WF_INSN(vfwadd);
19431971
DISASM_OPIV_WF_INSN(vfwsub);
19441972
DISASM_OPIV_VF_INSN(vfwmul);
1945-
DISASM_OPIV_VF_INSN(vfwmacc);
1946-
DISASM_OPIV_VF_INSN(vfwnmacc);
1947-
DISASM_OPIV_VF_INSN(vfwmsac);
1948-
DISASM_OPIV_VF_INSN(vfwnmsac);
1973+
DISASM_OPIV_MULTIPLYADD_VF_INSN(vfwmacc);
1974+
DISASM_OPIV_MULTIPLYADD_VF_INSN(vfwnmacc);
1975+
DISASM_OPIV_MULTIPLYADD_VF_INSN(vfwmsac);
1976+
DISASM_OPIV_MULTIPLYADD_VF_INSN(vfwnmsac);
19491977

19501978
#undef DISASM_OPIV_VF_INSN
19511979
#undef DISASM_OPIV__F_INSN

0 commit comments

Comments
 (0)