Compatibility with riscv v0.14.0, riscv-peripheral v0.3.0, and riscv-rt v0.15.0

Cargo.toml

@@ -4,4 +4,16 @@ members = [
     "e310x",
     "e310x-hal",
     "hifive1",
+    "hifive1-examples",
 ]
+default-members = [
+    "e310x",
+    "e310x-hal",
+    "hifive1",
+]
+
+[workspace.dependencies]
+critical-section = "1.2.0"
+riscv = { git = "https://github.com/rust-embedded/riscv.git", branch = "post-init" }
+riscv-peripheral = { git = "https://github.com/rust-embedded/riscv.git", branch = "post-init" }
+riscv-rt = { git = "https://github.com/rust-embedded/riscv.git", branch = "post-init", features = ["single-hart", "no-interrupts"] }

e310x-hal/CHANGELOG.md

@@ -7,6 +7,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Changed
+- Update `e310x` dependency and adapt code
+
 ## [v0.12.0] - 2024-12-10
 
 ### Changed

e310x-hal/Cargo.toml

@@ -16,8 +16,8 @@ embedded-hal-nb = "1.0.0"
 embedded-io = "0.6.1"
 e310x = { path = "../e310x", version = "0.12.0", features = ["rt", "critical-section"] }
 nb = "1.0.0"
-portable-atomic = { version = "1.9", default-features = false}
-riscv = { version = "0.12.1", features = ["critical-section-single-hart"] }
+portable-atomic = { version = "1.9", default-features = false }
+riscv = { workspace = true, features = ["critical-section-single-hart"] }
 
 [features]
 g002 = ["e310x/g002"]

e310x-hal/src/clock.rs

@@ -1,6 +1,6 @@
 //! Clock configuration
 use crate::time::Hertz;
-use e310x::{Aonclk as AONCLK, Prci as PRCI, CLINT};
+use e310x::{Aonclk as AONCLK, Clint, Prci as PRCI};
 use riscv::interrupt;
 use riscv::register::mcycle;
 
@@ -290,7 +290,7 @@ impl CoreClk {
         // Need to wait 100 us
         // RTC is running at 32kHz.
         // So wait 4 ticks of RTC.
-        let mtime = CLINT::mtimer().mtime;
+        let mtime = unsafe { Clint::steal() }.mtimer().mtime();
         let time = mtime.read() + 4;
         while mtime.read() < time {}
         // Now it is safe to check for PLL Lock
@@ -384,7 +384,7 @@ impl Clocks {
 
     /// Measure the coreclk frequency by counting the number of aonclk ticks.
     fn _measure_coreclk(&self, min_ticks: u64) -> Hertz {
-        let mtime = CLINT::mtimer().mtime;
+        let mtime = unsafe { Clint::steal() }.mtimer().mtime();
         interrupt::free(|| {
             // Don't start measuring until we see an mtime tick
             while mtime.read() == mtime.read() {}

e310x-hal/src/core/counters.rs

@@ -60,7 +60,7 @@ pub struct PerformanceCounters {
 }
 
 impl PerformanceCounters {
-    pub(crate) fn new() -> Self {
+    pub(crate) const fn new() -> Self {
         Self {
             mcycle: MCYCLE,
             minstret: MINSTRET,

e310x-hal/src/core/mod.rs

@@ -2,17 +2,23 @@
 
 pub mod counters;
 
-pub use e310x::{CLINT, PLIC};
+use e310x::{Clint, Plic};
 
 /// Core peripherals
 pub struct CorePeripherals {
+    /// Core Local Interruptor (CLINT)
+    pub clint: Clint,
+    /// Platform-Level Interrupt Controller (PLIC)
+    pub plic: Plic,
     /// Performance counters
     pub counters: counters::PerformanceCounters,
 }
 
 impl CorePeripherals {
-    pub(crate) fn new() -> Self {
+    pub(crate) const fn new(clint: Clint, plic: Plic) -> Self {
         Self {
+            clint,
+            plic,
             counters: counters::PerformanceCounters::new(),
         }
     }
@@ -23,6 +29,6 @@ impl CorePeripherals {
     ///
     /// Using this function may break the guarantees of the singleton pattern.
     pub unsafe fn steal() -> Self {
-        Self::new()
+        Self::new(Clint::steal(), Plic::steal())
     }
 }

e310x-hal/src/delay.rs

@@ -1,7 +1,7 @@
 //! # Delays
 
 use crate::clock::Clocks;
-use e310x::CLINT;
+use e310x::Clint;
 use embedded_hal::delay::DelayNs;
 use riscv::register::mip;
 
@@ -22,7 +22,7 @@ impl DelayNs for Delay {
     fn delay_ns(&mut self, ns: u32) {
         let ticks = (ns as u64) * TICKS_PER_SECOND / 1_000_000_000;
 
-        let mtime = CLINT::mtimer().mtime;
+        let mtime = unsafe { Clint::steal() }.mtimer().mtime();
         let t = mtime.read() + ticks;
         while mtime.read() < t {}
     }
@@ -45,12 +45,13 @@ impl Sleep {
 impl DelayNs for Sleep {
     fn delay_ns(&mut self, ns: u32) {
         let ticks = (ns as u64) * u64::from(self.clock_freq) / 1_000_000_000;
-        let t = CLINT::mtimer().mtime.read() + ticks;
+        let clint = unsafe { e310x::Clint::steal() };
+        let t = clint.mtimer().mtime().read() + ticks;
 
-        CLINT::mtimecmp0().write(t);
+        clint.mtimecmp0().write(t);
 
         // Enable timer interrupt
-        unsafe { CLINT::mtimer_enable() };
+        unsafe { clint.mtimer().enable() };
 
         // Wait For Interrupt will put CPU to sleep until an interrupt hits
         // in our case when internal timer mtime value >= mtimecmp value
@@ -66,6 +67,6 @@ impl DelayNs for Sleep {
         }
 
         // Clear timer interrupt
-        CLINT::mtimer_disable();
+        clint.mtimer().disable();
     }
 }

e310x-hal/src/device.rs

@@ -159,7 +159,7 @@ impl From<Peripherals> for DeviceResources {
         };
 
         DeviceResources {
-            core_peripherals: CorePeripherals::new(),
+            core_peripherals: CorePeripherals::new(p.clint, p.plic),
             peripherals,
             pins: p.gpio0.into(),
         }

e310x/CHANGELOG.md

@@ -11,7 +11,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - The I2C0 code is now gated under the `g002` feature
 - Regenerate code with `svd2rust` 0.36.1
-- Use `riscv` v0.13.0 and `riscv-rt` v0.14.0
+- Use `riscv` v0.14.0, `riscv-peripheral` v0.3.0, and `riscv-rt` v0.15.0
 - In vectored mode, align `mtvec` to 64 bytes
 
 ## [v0.12.0] - 2024-12-10

e310x/Cargo.toml

@@ -11,10 +11,10 @@ rust-version = "1.76"
 edition = "2021"
 
 [dependencies]
-critical-section = { version = "1.2.0", optional = true }
-riscv = "0.13.0"
-riscv-peripheral = "0.2.0"
-riscv-rt = { version = "0.14.0", features = ["no-interrupts"], optional = true }
+critical-section = { workspace = true, optional = true }
+riscv = { workspace = true }
+riscv-peripheral = { workspace = true }
+riscv-rt = { workspace = true, optional = true }
 vcell = "0.1.3"
 
 [features]

e310x/build.rs

@@ -12,7 +12,9 @@ fn main() {
             .unwrap();
         println!("cargo:rustc-link-search={}", out.display());
         println!("cargo:rerun-if-changed=device.x");
-        println!("cargo:rustc-env=RISCV_MTVEC_ALIGN={}", 64usize);
+        println!("cargo:rustc-env=RISCV_RT_BASE_ISA=rv32i");
+        println!("cargo:rerun-if-env-changed=RISCV_RT_BASE_ISA");
+        println!("cargo:rustc-env=RISCV_MTVEC_ALIGN=64");
         println!("cargo:rerun-if-env-changed=RISCV_MTVEC_ALIGN");
     }
     println!("cargo:rerun-if-changed=build.rs");

e310x/settings.yaml

@@ -43,12 +43,12 @@ riscv_config:
 
   clint:
     name: "CLINT"
-    freq: 32768
-    async_delay: false
+    mtime_freq: 32768
 
   plic:
     name: "PLIC"
     core_interrupt: "MachineExternal"
     hart_id: "H0"
 
+  base_isa: "rv32i"
   mtvec_align: 64

e310x/src/aonclk/lfrosccfg.rs

@@ -43,22 +43,22 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    pub fn div(&mut self) -> DivW<LfrosccfgSpec> {
+    pub fn div(&mut self) -> DivW<'_, LfrosccfgSpec> {
         DivW::new(self, 0)
     }
     #[doc = "Bits 16:20"]
     #[inline(always)]
-    pub fn trim(&mut self) -> TrimW<LfrosccfgSpec> {
+    pub fn trim(&mut self) -> TrimW<'_, LfrosccfgSpec> {
         TrimW::new(self, 16)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    pub fn enable(&mut self) -> EnableW<LfrosccfgSpec> {
+    pub fn enable(&mut self) -> EnableW<'_, LfrosccfgSpec> {
         EnableW::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    pub fn ready(&mut self) -> ReadyW<LfrosccfgSpec> {
+    pub fn ready(&mut self) -> ReadyW<'_, LfrosccfgSpec> {
         ReadyW::new(self, 31)
     }
 }