Add timing mitigation for implicit return and JTC - issue 206

branchTrace.adoc

@@ -336,7 +336,7 @@ traced rather than the target address. If it is not found in the cache,
 the entry at that index is replaced with the current instruction
 address.
 
-Note that if implicit return mode is enabled, most function return targets are  inferable and are not output in the trace.  Any such inferrable return target must not be stored in the cache.
+Note that if implicit return mode is enabled, most function return targets are  inferable and are not output in the trace.  Any such inferrable return target must not be stored in the cache.  This effectively puts the implicit return evaluation in series before the jump target cache, and this may present timing challenges.  This can be mitigated by invalidating the cache entry that corresponds to a mis-predicted return rather than updating the entry with the actual return address.  Mis-predicted returns are rare so the performance impact will be negligible. 
 
 The cache entries are all invalidated when a synchronization packet is
 sent.

discovery.adoc

@@ -42,7 +42,7 @@ supported when non_zero. Number of nested exceptions supported is
 1
 |_filter_tval_p_ | 0 or 1 | Filtering on trap value supported when 1
 (provided _filter_excint_p_ is non-zero)
-|_iaddress_lsb_p_ |  |  LSB of instruction *address* bus to trace. 1 is
+|_iaddress_lsb_p_ |  |  LSB of instruction *address* bus to trace. 1 if
 compressed instructions are supported, 2 otherwise
 |_iaddress_width_p_ |  |  Width of instruction *address* bus. This is the
 same as _DXLEN_