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Replace 'halted' signal with 'inhibit' vector #216

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Replace 'halted' signal with 'inhibit' vector #216

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2 changes: 1 addition & 1 deletion exampleAlgorithm.adoc
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Original file line number Diff line number Diff line change
Expand Up @@ -76,7 +76,7 @@ loaded into the buffer when space next becomes available must be a
_support_ packet. Following this, tracing will resume with a sync
packet.

Note: if the *halted* or *reset* sideband signals are asserted (see
Note: if the *inhibit* vector indicates tracing inhibition or *reset* signal is asserted (see
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As this will be a normative change, and will be version 2 of the HTI, we should also add a note indicating how to connect a hart with version 2 of the interface to an encoder with version 1. This can be accomplished by ORing the 2 bits of inhibit and connecting to halted.

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Sure, will add a note to suggest the connection. I am also thinking, is it a realistic case to have hart with version 1 connecting to encoder with version 2?

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Yes. For that case I think the relationship is more obvious, as the 'halted' output from the hart simply connects to bit 0 of inhibit, and bit 1 is tied low. Of course, any such system wouldn't have the ability to prevent tracing for security reasons. Or put another way, any hart implementing the secure debug extension must have a version 2 HTI.

<<tab:ingress-side-band>>) the encoder will behave as if it has received an unqualified instruction (output _te_inst_ reporting the address of the previous instruction, followed by
_te_support_);

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21 changes: 13 additions & 8 deletions ingressPort.adoc
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Expand Up @@ -436,14 +436,19 @@ signals. A typical use for these would be for filtering (see
encoder to start tracing, and continue until further notice, subject to
other filtering criteria also being met. A pulse on bit 1 will cause the
encoder to stop tracing until further notice. See <<sec:trigger>>).
|*halted* | O | Hart is halted. Upon assertion, the encoder will output a
packet to report the address of the last instruction retired before
halting, followed by a support packet to indicate that tracing has
stopped. Upon deassertion, the encoder will start tracing again,
commencing with a synchronization packet. *Note:* If this signal is not
provided, it is strongly recommended that Debug mode can be signalled
via a 3-bit *privilege* signal. This will allow tracing in Debug mode to
be controlled via the optional filtering capabilities.
|*inhibit*[1:0] | O | The 2-bit vector controls trace inhibition. When
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This looks fine. Because the line-breaks have moved the diff appears to show more changes than have actually been made. When the final PR against HTI is done, please try to retain as many of the existing line breaks as possible.

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Thanks! Will pay attention to it.

inhibited, the encoder will output a packet to report the address of the
last instruction retired before inhibition, followed by a support packet
to indicate that tracing has stopped. Upon resumption, the encoder will
start tracing again, commencing with a synchronization packet. +
00: Tracing allowed +
01: Tracing inhibited due to hart being halted +
10: Tracing inhibited due to security violation +
11: Reserved +
*Note:* If this vector is not provided, it is strongly recommended that
Debug mode can be signalled via a 3-bit *privilege* signal. This will
allow tracing in Debug mode to be controlled via the optional filtering
capabilities.
|*reset* | O | Hart is in reset. Provided the encoder is in a different
reset domain to the hart, this allows the encoder to indicate that
tracing has ended on entry to reset, and restarted on exit. Behavior is
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