Clarified sync-trap behaviour if 1st traced instruction traps - Issue…

header.adoc

@@ -54,15 +54,15 @@ endif::[]
 - Corrected reference decoder in <<Decoder>> to cover a corner-case related to trap returns.
 |05-Mar-2024 |First version in AsciiDoc format.
 |19-Apr-2024 |Formatting and typo fixes.
-|TBD |
-- Minor clarifications, formatting and typo fixes.  +
-- Updated <<packets>> and <<fragments>> to reference the https://github.com/riscv-non-isa/e-trace-encap/releases/latest/[Unformatted Trace & Diagnostic Data Packet Encapsulation for RISC-V Specification] +
-- Removed ambiguity between 'last' and 'final'.  Last was previously used to mean both the instruction before the current one, and the final instruction traced. +
-- Clarified behaviour when trace-on and trace-off triggers occur both occur in the same cycle (see <<sec:trigger>>) +
-- Clarified that full synchronization also takes place on a privilege change (see <<sec:synchronization>> and <<sec:thaddr>>) +
-- Reworded jump classifications in jump classifications in <<sec:InstructionInterfaceRequirements>> to align with terminology used in other specifications +
-- Clarified when to issue sync-support packet when trace is enabled (see <<sec:format33>>) +
-- Updated reference encoding algorithm to generalize resync behaviour and add missing trap conditions (see <<Algorithm>>)
+|This edition |
+- Minor clarifications, formatting and typo fixes;  +
+- Updated <<packets>> and <<fragments>> to reference the https://github.com/riscv-non-isa/e-trace-encap/releases/latest/[Unformatted Trace & Diagnostic Data Packet Encapsulation for RISC-V Specification]; +
+- Removed ambiguity between 'last' and 'final'.  Last was previously used to mean both the instruction before the current one, and the final instruction traced; +
+- Clarified behaviour when trace-on and trace-off triggers occur both occur in the same cycle (see <<sec:trigger>>); +
+- Clarified that full synchronization also takes place on a privilege change (see <<sec:synchronization>> and <<sec:thaddr>>); +
+- Reworded jump classifications in jump classifications in <<sec:InstructionInterfaceRequirements>> to align with terminology used in other specifications; +
+- Clarified when to issue sync-support packet when trace is enabled (see <<sec:format33>>); +
+- Updated reference encoding algorithm to generalize resync behaviour and add missing trap conditions (see <<Algorithm>>).
 
 |===
 

payload.adoc

@@ -163,7 +163,7 @@ If an exception occurs at the target of an uninferable PC discontinuity,
 the value of the EPC cannot be infered from the program binary, and so
 *address* contains the EPC and *thaddr* is set to 0. In this case, the
 trap handler address will be reported via a subsequent format 3,
-subformat 0 packet.
+subformat 0 packet.  An exception occuring on the 1st traced instruction is treated in the same way.
 
 Usually when an exception or interrupt occurs, the cause is reported
 along with the 1st address of the trap handler, when that instruction