Updates 2.0.4 issue 187

exampleAlgorithm.adoc

@@ -9,7 +9,7 @@ A reference algorithm for compressed branch trace is given in
 * _te_inst._ The name of the packet type emitted by the encoder (see
 <<packets>>);
 * _inst._ Abbreviation for 'instruction';
-* _exception. Exception or interrupt signalled;_
+* _trap. Exception or interrupt signalled;_
 * _updiscon._ Uninferable PC discontinuity. This identifies an
 instruction that causes the program counter to be changed by an amount
 that cannot be predicted from the source code alone (*itype* values 8,
@@ -24,21 +24,15 @@ not;
 reported precisely or treated as an uninferable PC discontinuity (see
 <<tab:context-type>>);
 * _ppccd_br._ As above, but branch map not empty;
-* _er_n._ Instruction retirement and exception signalled on the same
-cycle, or Trace notify trigger (see
-<<tab:debugModuleTriggerSupport>>);
-* _exc_only._ Exception or interrupt signalled without simultaneous
-retirement;
+* _ntf._ Trace notify trigger (see <<tab:debugModuleTriggerSupport>>);
 * _cci._ context change that can be reported imprecisely (see
 <<tab:context-type>>);
 * _rpt_br._ Report branches due to full branch map or misprediction;
 * _branches._ The number of branches encountered but not yet reported to
 the decoder;
 * _pbc._ Correctly predicted branches count (always zero if branch
 predictor disabled or not present);
-* _Reported?_ "Exception previous" reported with *thaddr* = 0 on the
-cycle it occured because it was preceded by an updiscon or immediately
-followed by another exception;
+* _trep_ Previous trap already reported with *thaddr* = 0 because it was preceded by an updiscon or immediately followed by another exception;
 * _resync count._ A counter used to keep track of when it is necessary
 to send a synchronization packet (see <<sec:resync>>);
 * _max_resync._ The resync counter value that schedules a
@@ -52,7 +46,7 @@ would be seen in a single-retirement system only. Whilst the core to
 encoder interface allows the RISC-V hart to provide information on
 multiple retiring instructions simultaneously, the resultant packet
 sequence generated by the encoder must be the same as if retiring one
-instruction at a time.
+instruction at a time.  Note that even with a single-retirement system it is possible to retire an instruction and report a trap simultaneously (*itype* = 1 or 2 and *iretire* = 1).  In this case the flow diagram must be traversed twice, first for the retired instruction, and then for the trap.
 
 A 3-stage pipeline within the encoder is assumed, such that the encoder
 has visibility of the current, previous and next instructions. All

header.adoc

@@ -2,8 +2,8 @@
 Gajinder Panesar <gajinder.panesar@gmail.com>, Iain Robertson <iain.robertson@siemens.com>
 :description: Efficient Trace for RISC-V
 :company: RISC-V.org
-:revdate: April 19, 2024
-:revnumber: 2.0.3
+:revdate: TBD, 2024
+:revnumber: 2.0
 :url-riscv: http://riscv.org
 :doctype: book
 :pdf-theme: docs-resources/themes/riscv-pdf.yml
@@ -46,14 +46,15 @@ endif::[]
 [%autowidth,align="center",float="center",cols="<,<",options="header"]
 |===
 |2.0|Baseline
-|2.0.1 |Clarifications only - no changes to normative behaviour. +
+|15-Dec-2023 |Clarifications only - no changes to normative behaviour. +
 - Control field definitions removed from section 2, which now references the xref:https://github.com/riscv-non-isa/tg-nexus-trace/blob/master/docs/RISC-V-Trace-Control-Interface.adoc[RISC-V Trace Control Interface Specification] +
 - Added detail on handling of multi-load/store instructions for data trace to <<sec:DataInterfaceRequirements>>. +
 - Removed references to tail-calls in jump classifications in <<sec:InstructionInterfaceRequirements>>. +
 - Corrected typos where `lrid` was inadvertently refered to by an earlier name (`index`) in <<sec:data-loadstore>>. +
 - Corrected reference decoder in <<Decoder>> to cover a corner-case related to trap returns.
-|2.0.2 |First version in AsciiDoc format.
-|2.0.3 |Formatting and typo fixes.
+|05-Mar-2024 |First version in AsciiDoc format.
+|19-Apr-2024 |Formatting and typo fixes.
+|TBD |Details to follow.
 |===
 
 [preface]

ingressPort.adoc

@@ -306,7 +306,7 @@ block.
 *itype* can be 3 or 4 bits wide. If _itype_width_p_ is 3, a single code
 (6) is used to indicate all uninferable jumps. This is simpler to
 implement, but precludes use of the implicit return mode (see
-<<sec:implicit-return>>), which requires jump types to be fully classified.
+<<sec:implicit-return>>), which requires jump types to be fully classified.    
 
 Whilst *iaddr* is typically a virtual address, it does not affect the
 encoder's behavior if it is a physical address.