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2 changes: 1 addition & 1 deletion branchTrace.adoc
Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,7 @@ result of a specific instruction or event. Exceptions can be thought of
in the same way, even though they can be typically linked back to a
specific instruction address.

The decoder generally does not know where an interrupt occured in the
The decoder generally does not know where an interrupt occurred in the
instruction sequence, so the trace must report the address where normal
program flow ceased, as well as give an indication of the asynchronous
destination which may be as simple as reporting the exception type. When
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2 changes: 1 addition & 1 deletion exampleAlgorithm.adoc
Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,7 @@ the decoder;
* _pbc._ Correctly predicted branches count (always zero if branch
predictor disabled or not present);
* _Reported?_ "Exception previous" reported with *thaddr* = 0 on the
cycle it occured because it was preceded by an updiscon or immediately
cycle it occurred because it was preceded by an updiscon or immediately
followed by another exception;
* _resync count._ A counter used to keep track of when it is necessary
to send a synchronization packet (see <<sec:resync>>);
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2 changes: 1 addition & 1 deletion ingressPort.adoc
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Expand Up @@ -151,7 +151,7 @@ can be connected to a separate encoder instance, allowing all harts to
be traced concurrently. Alternatively, external muxing may be used in
conjunction with a single encoder in order to trace one particular hart
at a time;
* Implement a singe interface for the core, with muxing inside the core
* Implement a single interface for the core, with muxing inside the core
to select which hart to connect to the interface.

(Whilst it is technically feasible to use a single encoder with multiple
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