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Clarify which addresses are stored in the JTC - Issue 169 #171

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Feb 18, 2025
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Clarify which addresses are stored in the JTC - Issue 169 #171

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Clarify which addresses are stored in the JTC - Issue 169
IainCRobertson Nov 12, 2024
2abfe81
Further clarifications
IainCRobertson Nov 12, 2024
161b693
Updating revision history for Issue 169
IainCRobertson Feb 18, 2025
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6 changes: 3 additions & 3 deletions branchTrace.adoc
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Expand Up @@ -331,12 +331,12 @@ cache with identical behavior will need to be implemented in the decoder
software. Even a small cache can provide significant improvement.

The cache shall comprise 2^_cache_size_p_^ entries, each of which can
contain an instruction address. It will be direct mapped, with each
contain an instruction address. The addresses stored in the cache are
the targets of uninferable jumps. It will be direct mapped, with each
entry indexed by bits _cache_size_p_:1 of the instruction address (or
__cache_size_p__+1:2 if compressed instructions aren't supported).

Each uninferable jump target is first compared with the entry at its
index in the cache. If it is found in the cache, the index number is
Each uninferable jump target is first compared with the entry in the cache at the index derived from the jump target address. If it is found in the cache, the index number is
traced rather than the target address. If it is not found in the cache,
the entry at that index is replaced with the current instruction
address.
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