PMM (Pointer Masking) ACTs

[UmerShahidengr]

Description

This PR has ACTs for Pointer Masking Extension

Ratified/Unratified Extensions

• Ratified
• [] Unratified

List Extensions

Pointer Masking Extension specs (frozen) : available here
Sail PR: available here

Reference Model Used

• SAIL
• Spike
• Other - < SPECIFY HERE >

Mandatory Checklist:

• All tests are compliant with the test-format spec present in this repo ?
• Ran the new tests on RISCOF with SAIL/Spike as reference model successfully ?
• Ran the new tests on RISCOF in coverage mode
• Link to Google-Drive folder containing the new coverage reports (See this for more info): < SPECIFY HERE >
• Link to PR in RISCV-ISAC from which the reports were generated : < SPECIFY HERE >
• Changelog entry created with a minor patch

Optional Checklist:

• RISCV-V CTG PR link if tests were generated using it : < SPECIFY HERE >
• Were the tests hand-written/modified ?
• Have you run these on any hard DUT model ? Please specify name and provide link if possible in the description
• If you have modified arch_test.h Please provide a detailed description of the changes in the Description section above.

[MuhammadHammad001]

Hi,
This SOW is complete. All the tests with 100% coverage are added in this PR(access the coverage report here).
@allenjbaum @jamesbeyond @UmerShahidengr

[MuhammadHammad001]

To run the coverage locally, use the following command:

riscof coverage --config=/home/hammad//riscv-arch-test/config.ini --cgf-file=/home/hammad/riscv-arch-test/coverage/dataset.cgf --cgf-file=/home/hammad/Pointer_Masking/sir_umer_repo/riscv-arch-test/coverage/rv64_pmm.cgf --suite=/home/hammad/riscv-test-suite/rv64i_m/pmm --env=/home/hammad/artifacts/env -h /home/hammad/riscv-arch-test/coverage/header_file.yaml

[nadime15]

Hi all!

I am currently using these tests to validate the implementation of the pointer masking extension for Sail.

I have come across a few issues that I wanted to share:

1. The default configuration in Sail doesn't work as-is, you will encounter a load-access-fault (PMM_basic_01_M_sv48_tag11.S).

0x00000000800007A4 (0x00040483) lb x9, 0x0(x8)
mem[R,0x0000000080006900] -> 0x00200000000000DF
within_phys_mem: 0x0080000000000000 not within phys-mem:
  plat_rom_base: 0x0000000000001000
  plat_rom_size: 0x0000000000001000
  plat_ram_base: 0x0000000080000000
  plat_ram_size: 0x0000000080000000
trapping from M to M to handle load-access-fault

this is due to the size of the RAM, which is for these tests to small, changing the configuration and increasing the RAM size (in my case to 8 exabyte) will get rid of the problem:

"ram": {
  "base": 2147483648,
  "size": 9223372036854775808
}

2. Spike will also "fail" with an illegal instruction exception. This happens because the Smmpm extension is not enabled (btw. all extensions, namely Smnpm, Smmpm and Ssnpm should be enabled), which is required for accessing the mseccfg CSR (PMM_basic_01_M_sv48_tag11.S):

core   0: 0x0000000080000818 (0x7476a073) csrs    mseccfg, a3
core   0: exception trap_illegal_instruction, epc 0x0000000080000818
core   0:           tval 0x000000007476a073

Snippet from Spike:

void mseccfg_csr_t::verify_permissions(insn_t insn, bool write) const {
  basic_csr_t::verify_permissions(insn, write);
  if (!proc->extension_enabled(EXT_SMEPMP) &&
      !proc->extension_enabled(EXT_SMMPM) &&
      !proc->extension_enabled(EXT_ZICFILP) &&
      !proc->extension_enabled(EXT_ZKR))
    throw trap_illegal_instruction(insn.bits());
}

I believe there are a few more issues that still need to be resolved, and I am currently investigating their root causes.

[MuhammadHammad001]

@nadime15 Thank you for pointing out the issues. This is a really old PR and the sail model has changed a lot since then.

I will update the changes in the next commit.