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Merge pull request #371 from ved-rivos/svadu1
Add ratified Svadu extension
2 parents 034f1cc + 09771ee commit ac2bffa

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-17
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9 files changed

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‎CHANGELOG.md

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,8 @@
11
# CHANGELOG
2-
## [3.8.18] - 2023-07-28
2+
## [3.8.19] - 2024-05-08
3+
- Add support for unratified Svadu extension
4+
5+
## [3.8.18] - 2024-05-08
36
- Add Zacas ISA extension support.
47

58
## [3.8.17] - 2024-05-03
@@ -100,6 +103,9 @@ Add missing check ISA fields in recently modified div and amo tests
100103
- Add ACTs for Atomic Extension excluding Lr/Sc Instructions.
101104
- Added Test macro for the execution of atomic instructions.
102105

106+
## [3.7.1] - 2023-07-30
107+
- Add support for unratified Svadu extension
108+
103109
## [3.7.0] - 2023-05-16
104110
- Updated the LI macro
105111
- Make Trap handler compatible for RV32E

‎coverage/rv32_svadu.cgf

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
2+
svhad_sv32:
3+
config:
4+
- check ISA:=regex(.*I.*Svhad.*)
5+
opcode:
6+
nop: 0
7+
8+

‎coverage/rv64_svadu.cgf

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
svhad_sv39:
2+
config:
3+
- check ISA:=regex(.*I.*Svhad.*)
4+
opcode:
5+
nop: 0
6+
7+
svhad_sv48:
8+
config:
9+
- check ISA:=regex(.*I.*Svhad.*)
10+
opcode:
11+
nop: 0
12+
13+
svhad_sv57:
14+
config:
15+
- check ISA:=regex(.*I.*Svhad.*)
16+
opcode:
17+
nop: 0

‎riscv-test-suite/env/encoding.h

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -131,6 +131,18 @@
131131
#define SIP_SSIP MIP_SSIP
132132
#define SIP_STIP MIP_STIP
133133

134+
#define MENVCFG_FIOM 0x00000001
135+
#define MENVCFG_CBIE 0x00000030
136+
#define MENVCFG_CBCFE 0x00000040
137+
#define MENVCFG_CBZE 0x00000080
138+
#define MENVCFG_ADUE 0x2000000000000000
139+
#define MENVCFG_PBMTE 0x4000000000000000
140+
#define MENVCFG_STCE 0x8000000000000000
141+
142+
#define MENVCFGH_ADUE 0x20000000
143+
#define MENVCFGH_PBMTE 0x40000000
144+
#define MENVCFGH_STCE 0x80000000
145+
134146
#define PRV_U 0
135147
#define PRV_S 1
136148
#define PRV_H 2

‎riscv-test-suite/env/test_macros.h

Lines changed: 189 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,127 @@
3030
#define SIG sig_bgn_off
3131
#define VMEM vmem_bgn_off
3232

33+
34+
#define SATP_SETUP(_TR0, _TR1, MODE);\
35+
LA(_TR0, rvtest_Sroot_pg_tbl) ;\
36+
LI(_TR1, MODE) ;\
37+
srli _TR0, _TR0, 12 ;\
38+
or _TR0, _TR0, _TR1 ;\
39+
csrw satp, _TR0 ;\
40+
41+
#define SETUP_PMP_SVADU_TEST(swreg, offset, TR0, TR1, TR2) \
42+
li TR0, -1 ;\
43+
csrw pmpaddr0, TR0 ;\
44+
j PMP_exist ;\
45+
li TR0, 0 ;\
46+
li TR1, 0 ;\
47+
j Mend_PMP ;\
48+
PMP_exist: ;\
49+
li TR1, PMP_TOR | PMP_X | PMP_W | PMP_R ;\
50+
csrw pmpcfg0, TR1 ;\
51+
csrr TR2, pmpcfg0 ;\
52+
beq TR1, TR2, Mend_PMP ;\
53+
no_TOR_try_NAPOT: ;\
54+
li TR1, PMP_NAPOT | PMP_X | PMP_W | PMP_R ;\
55+
csrw pmpcfg0, TR1 ;\
56+
csrr TR2, pmpcfg0 ;\
57+
Mend_PMP: ;\
58+
RVTEST_SIGUPD(x1,TR0,offset) ;\
59+
RVTEST_SIGUPD(x1,TR1,offset) ;\
60+
61+
#define TEST_SVADU(swreg, PTE_ADDR, VA, offset, menvcfgaddr, adue_bit) \
62+
sfence.vma ;\
63+
la t0, VA ;\
64+
li t2, PTE_X | PTE_W | PTE_R ;\
65+
1: ;\
66+
LREG t1, (PTE_ADDR) ;\
67+
andi t1, t1, ~(PTE_X | PTE_W | PTE_R | PTE_V) ;\
68+
or t1, t1, t2 ;\
69+
SREG t1, (PTE_ADDR) ;\
70+
sfence.vma ;\
71+
;\
72+
li t1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM | MSTATUS_MPRV ;\
73+
csrs mstatus, t1 ;\
74+
;\
75+
.align 2 ;\
76+
SREG x0, (t0) ;\
77+
unimp ;\
78+
;\
79+
li t1, MSTATUS_MPRV ;\
80+
csrc mstatus, t1 ;\
81+
;\
82+
beqz t2, 2f ;\
83+
addi t2, t2, -1 ;\
84+
li t1, PTE_W | PTE_R | PTE_V ;\
85+
bne t2, t1, 1b ;\
86+
addi t2, t2, -1 ;\
87+
j 1b ;\
88+
2: ;\
89+
li t0, MSTATUS_MPRV ;\
90+
csrc mstatus, t0 ;\
91+
LREG t0, (PTE_ADDR) ;\
92+
and t0, t0, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D ;\
93+
RVTEST_SIGUPD(x1,t0,offset) ;\
94+
;\
95+
LREG t0, (PTE_ADDR) ;\
96+
andi t0, t0, ~(PTE_X | PTE_W | PTE_R | PTE_V | PTE_A | PTE_D | PTE_V) ;\
97+
ori t0, t0, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A ;\
98+
SREG t0, (PTE_ADDR) ;\
99+
sfence.vma ;\
100+
;\
101+
la t0, VA ;\
102+
li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM | MSTATUS_MPRV ;\
103+
csrs mstatus, a1 ;\
104+
;\
105+
.align 2 ;\
106+
SREG x0, (t0) ;\
107+
unimp ;\
108+
;\
109+
li t0, MSTATUS_MPRV ;\
110+
csrc mstatus, t0 ;\
111+
;\
112+
LREG t0, (PTE_ADDR) ;\
113+
and t0, t0, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D ;\
114+
RVTEST_SIGUPD(x1,t0,offset) ;\
115+
;\
116+
LREG t0, (PTE_ADDR) ;\
117+
andi t0, t0, ~(PTE_X | PTE_W | PTE_R | PTE_V | PTE_A | PTE_D | PTE_V) ;\
118+
ori t0, t0, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D ;\
119+
SREG t0, (PTE_ADDR) ;\
120+
sfence.vma ;\
121+
la t0, VA ;\
122+
li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM | MSTATUS_MPRV ;\
123+
csrs mstatus, a1 ;\
124+
;\
125+
SREG x0, (t0) ;\
126+
j 3f ;\
127+
unimp ;\
128+
3: ;\
129+
LREG t0, (PTE_ADDR) ;\
130+
andi t0, t0, ~(PTE_D) ;\
131+
SREG t0, (PTE_ADDR) ;\
132+
sfence.vma ;\
133+
;\
134+
li t0, adue_bit ;\
135+
csrs menvcfgaddr, t0 ;\
136+
;\
137+
la t0, VA ;\
138+
li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM | MSTATUS_MPRV ;\
139+
csrs mstatus, a1 ;\
140+
;\
141+
.align 2 ;\
142+
SREG x0, (t0) ;\
143+
j 4f ;\
144+
unimp ;\
145+
4: ;\
146+
li t0, MSTATUS_MPRV ;\
147+
csrc mstatus, t0 ;\
148+
;\
149+
LREG t0, (PTE_ADDR) ;\
150+
and t0, t0, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D ;\
151+
RVTEST_SIGUPD(x1,t0,offset)
152+
153+
33154
#define ALL_MEM_PMP ;\
34155
li t2, -1 ;\
35156
csrw pmpaddr0, t2 ;\
@@ -55,23 +176,74 @@
55176

56177
//****NOTE: label `rvtest_Sroot_pg_tbl` must be declared after RVTEST_DATA_END
57178
// in the test aligned at 4kiB (use .align 12)
58-
59-
#define PTE_SETUP_RV32(_PAR, _PR, _TR0, _TR1, VA, level) ;\
60-
srli _PAR, _PAR, 12 ;\
61-
slli _PAR, _PAR, 10 ;\
62-
or _PAR, _PAR, _PR ;\
63-
.if (level==1) ;\
64-
LA(_TR1, rvtest_Sroot_pg_tbl) ;\
65-
.set vpn, ((VA>>22)&0x3FF)<<2 ;\
66-
.endif ;\
67-
.if (level==0) ;\
68-
LA(_TR1, rvtest_slvl1_pg_tbl) ;\
69-
.set vpn, ((VA>>12)&0x3FF)<<2 ;\
70-
.endif ;\
71-
LI(_TR0, vpn) ;\
72-
add _TR1, _TR1, _TR0 ;\
179+
#define PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\
180+
srli _VAR, _VAR, (RISCV_PGLEVEL_BITS * level + RISCV_PGSHIFT) ;\
181+
srli _PAR, _PAR, (RISCV_PGLEVEL_BITS * level + RISCV_PGSHIFT) ;\
182+
slli _PAR, _PAR, (RISCV_PGLEVEL_BITS * level + RISCV_PGSHIFT) ;\
183+
LI(_TR0, ((1 << RISCV_PGLEVEL_BITS) - 1)) ;\
184+
and _VAR, _VAR, _TR0 ;\
185+
slli _VAR, _VAR, ((XLEN >> 5)+1) ;\
186+
add _TR1, _TR1, _VAR ;\
187+
srli _PAR, _PAR, 12 ;\
188+
slli _PAR, _PAR, 10 ;\
189+
or _PAR, _PAR, _PR ;\
73190
SREG _PAR, 0(_TR1);
74191

192+
#define PTE_SETUP_SV32(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\
193+
.if (level==1) ;\
194+
LA(_TR1, rvtest_Sroot_pg_tbl) ;\
195+
.endif ;\
196+
.if (level==0) ;\
197+
LA(_TR1, rvtest_slvl1_pg_tbl) ;\
198+
.endif ;\
199+
PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level)
200+
201+
#define PTE_SETUP_SV39(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\
202+
.if (level==2) ;\
203+
LA(_TR1, rvtest_Sroot_pg_tbl) ;\
204+
.endif ;\
205+
.if (level==1) ;\
206+
LA(_TR1, rvtest_slvl2_pg_tbl) ;\
207+
.endif ;\
208+
.if (level==0) ;\
209+
LA(_TR1, rvtest_slvl1_pg_tbl) ;\
210+
.endif ;\
211+
PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level)
212+
213+
#define PTE_SETUP_SV48(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\
214+
.if (level==3) ;\
215+
LA(_TR1, rvtest_Sroot_pg_tbl) ;\
216+
.endif ;\
217+
.if (level==2) ;\
218+
LA(_TR1, rvtest_slvl3_pg_tbl) ;\
219+
.endif ;\
220+
.if (level==1) ;\
221+
LA(_TR1, rvtest_slvl2_pg_tbl) ;\
222+
.endif ;\
223+
.if (level==0) ;\
224+
LA(_TR1, rvtest_slvl1_pg_tbl) ;\
225+
.endif ;\
226+
PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level)
227+
228+
#define PTE_SETUP_SV57(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\
229+
.if (level==4) ;\
230+
LA(_TR1, rvtest_Sroot_pg_tbl) ;\
231+
.endif ;\
232+
.if (level==3) ;\
233+
LA(_TR1, rvtest_slvl4_pg_tbl) ;\
234+
.endif ;\
235+
.if (level==2) ;\
236+
LA(_TR1, rvtest_slvl3_pg_tbl) ;\
237+
.endif ;\
238+
.if (level==1) ;\
239+
LA(_TR1, rvtest_slvl2_pg_tbl) ;\
240+
.endif ;\
241+
.if (level==0) ;\
242+
LA(_TR1, rvtest_slvl1_pg_tbl) ;\
243+
.endif ;\
244+
PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level)
245+
246+
75247
#define PTE_SETUP_RV64(_PAR, _PR, _TR0, _TR1, VA, level, mode) ;\
76248
srli _PAR, _PAR, 12 ;\
77249
slli _PAR, _PAR, 10 ;\
@@ -151,6 +323,7 @@
151323
or _TR0, _TR0, _PR ;\
152324
SREG _TR0, 0(_TR1) ;
153325

326+
154327
#define SATP_SETUP_SV32 ;\
155328
LA(t6, rvtest_Sroot_pg_tbl) ;\
156329
LI(t5, SATP32_MODE) ;\
@@ -189,7 +362,6 @@
189362
RVTEST_SIGUPD(sigptr, destreg) /* write original AMO val */
190363

191364

192-
193365
#define NAN_BOXED(__val__,__width__,__max__) ;\
194366
.if __width__ == 16 ;\
195367
.hword __val__ ;\
@@ -1099,6 +1271,7 @@ ADDI(swreg, swreg, RVMODEL_CBZ_BLOCKSIZE)
10991271
sub x1,x1,tempreg ;\
11001272
RVTEST_SIGUPD(swreg,x1,offset)
11011273

1274+
11021275
// for updating signatures of Zacas paired destination register (RV32/RV64).
11031276
#define RVTEST_SIGUPD_PZACAS(_BR,_R1,_R2,...) ;\
11041277
.if NARG(__VA_ARGS__) == 1 ;\

‎riscv-test-suite/rv32i_m/Svadu/src/svadu_sv32.S

Lines changed: 76 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,76 @@
1+
// -----------
2+
// Copyright (c) 2020. RISC-V International. All rights reserved.
3+
// SPDX-License-Identifier: BSD-3-Clause
4+
// -----------
5+
//
6+
// This assembly file tests the Svadu extension
7+
//
8+
#include "model_test.h"
9+
#include "arch_test.h"
10+
11+
# Test Virtual Machine (TVM) used by program.
12+
RVTEST_ISA("RV32I_Zicsr")
13+
14+
# Test code region
15+
.section .text.init
16+
.globl rvtest_entry_point
17+
rvtest_entry_point:
18+
RVMODEL_BOOT
19+
RVTEST_CODE_BEGIN
20+
21+
#ifdef TEST_CASE_1
22+
RVTEST_CASE(1,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);check ISA:=regex(.*Svadu.*);def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",svadu_sv32)
23+
24+
RVTEST_SIGBASE(x1, signature_x1_0)
25+
26+
# Setup PMP to cover 4G of address space
27+
SETUP_PMP_SVADU_TEST(x1, offset, t0, t1, t2)
28+
29+
# Identity map the page_4k
30+
la t1, page_4k
31+
mv t2, t1
32+
PTE_SETUP_SV32(t1, PTE_V, t0, s2, t2, 1)
33+
34+
# enable virtual memory in Sv32 mode
35+
SATP_SETUP(t0, t1, SATP32_MODE)
36+
37+
# test svadu
38+
TEST_SVADU(x1, s2, page_4k, offset, 0x31a, MENVCFGH_ADUE)
39+
40+
#endif
41+
RVTEST_CODE_END
42+
RVMODEL_HALT
43+
44+
RVTEST_DATA_BEGIN
45+
.align 12
46+
page_4k:
47+
.fill 4096/REGWIDTH, REGWIDTH, 0
48+
RVTEST_DATA_END
49+
50+
.align 12
51+
rvtest_Sroot_pg_tbl:
52+
.fill 4096/REGWIDTH, REGWIDTH, 0
53+
54+
# Output data section.
55+
RVMODEL_DATA_BEGIN
56+
rvtest_sig_begin:
57+
sig_begin_canary:
58+
CANARY;
59+
60+
signature_x1_0:
61+
.fill 128*(XLEN/32),4,0xdeadbeef
62+
63+
#ifdef rvtest_mtrap_routine
64+
mtrap_sigptr:
65+
.fill 128*4, 4, 0xdeadbeef
66+
#endif
67+
68+
#ifdef rvtest_gpr_save
69+
gpr_save:
70+
.fill 32*(XLEN/32), 4, 0xdeadbeef
71+
#endif
72+
73+
sig_end_canary:
74+
CANARY;
75+
rvtest_sig_end:
76+
RVMODEL_DATA_END

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