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UmerShahidengrUmerShahidengr
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Merge pull request #370 from ved-rivos/zacas
Add ratified Zacas extension
2 parents 67c5e71 + c9d9a3f commit 034f1cc

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‎CHANGELOG.md

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@@ -1,4 +1,6 @@
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# CHANGELOG
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## [3.8.18] - 2023-07-28
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- Add Zacas ISA extension support.
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## [3.8.17] - 2024-05-03
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- Add Zfa support.
@@ -117,6 +119,7 @@ Add missing check ISA fields in recently modified div and amo tests
117119
- Added test case for division if most negative number by -1
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- Solved the [issue #300](https://github.com/riscv-non-isa/riscv-arch-test/issues/300)
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## [3.7.0] - 2023-05-16
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- Updated the LI macro
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- Make Trap handler compatible for RV32E

‎coverage/dataset.cgf

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@@ -144,6 +144,23 @@ datasets:
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x30: 0
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x31: 0
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pair_regs: &pair_regs
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x2: 0
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x4: 0
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x6: 0
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x8: 0
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x10: 0
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x12: 0
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x14: 0
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x16: 0
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x18: 0
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x20: 0
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x22: 0
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x24: 0
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x26: 0
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x28: 0
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x30: 0
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cbfmt_immval_sgn: &cbfmt_immval_sgn
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'imm_val == (-2**(6-1))': 0
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'imm_val == 0': 0
@@ -321,3 +338,93 @@ datasets:
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'walking_zeros("imm_val", 12,False)': 0
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'alternate("imm_val",12,False)': 0
323340

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rvp64_rs1val_sgn: &rvp64_rs1val_sgn
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'rs1_val == (-2**63)': 0
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'rs1_val == 0': 0
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'rs1_val == (2**63-1)': 0
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'rs1_val == 1': 0
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rvp64_rs2val_sgn: &rvp64_rs2val_sgn
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'rs2_val == (-2**63)': 0
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'rs2_val == 0': 0
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'rs2_val == (2**63-1)': 0
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'rs2_val == 1': 0
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rvp64_rs1val_unsgn: &rvp64_rs1val_unsgn
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'rs1_val == 0': 0
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'rs1_val == (2**64-1)': 0
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'rs1_val == 1': 0
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rvp64_rs2val_unsgn: &rvp64_rs2val_unsgn
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'rs2_val == 0': 0
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'rs2_val == (2**64-1)': 0
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'rs2_val == 1': 0
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rvp64_rs1val_walking_sgn: &rvp64_rs1val_walking_sgn
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'walking_ones("rs1_val", 64)': 0
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'walking_zeros("rs1_val", 64)': 0
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'alternate("rs1_val",64)': 0
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rvp64_rs2val_walking_sgn: &rvp64_rs2val_walking_sgn
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'walking_ones("rs2_val", 64)': 0
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'walking_zeros("rs2_val", 64)': 0
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'alternate("rs2_val",64)': 0
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rvp64_rs1val_walking_unsgn: &rvp64_rs1val_walking_unsgn
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'walking_ones("rs1_val", 64, signed=False)': 0
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'walking_zeros("rs1_val", 64, signed=False)': 0
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'alternate("rs1_val",64, signed=False)': 0
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rvp64_rs2val_walking_unsgn: &rvp64_rs2val_walking_unsgn
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'walking_ones("rs2_val", 64, signed=False)': 0
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'walking_zeros("rs2_val", 64, signed=False)': 0
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'alternate("rs2_val",64, signed=False)': 0
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rvp128_rs1val_sgn: &rvp128_rs1val_sgn
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'rs1_val == 0': 0
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'rs1_val == 1': 0
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rvp128_rs2val_sgn: &rvp128_rs2val_sgn
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'rs2_val == 0': 0
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'rs2_val == 1': 0
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rvp128_rs1val_walking_sgn: &rvp128_rs1val_walking_sgn
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'walking_ones("rs1_val", 128)': 0
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'walking_zeros("rs1_val", 128)': 0
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'alternate("rs1_val",128)': 0
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rvp128_rs2val_walking_sgn: &rvp128_rs2val_walking_sgn
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'walking_ones("rs2_val", 128)': 0
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'walking_zeros("rs2_val", 128)': 0
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'alternate("rs2_val",128)': 0
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zacas_op_comb: &zacas_op_comb
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'rs1 != rs2 and rs1 != rd and rs2 != rd': 0
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zacas_dcas_rs1val_sgn: &zacas_dcas_rs1val_sgn
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'rs1_val == 0': 0
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'rs1_val == 1': 0
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zacas_dcas_rs2val_sgn: &zacas_dcas_rs2val_sgn
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'rs2_val == 0': 0
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'rs2_val == 1': 0
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zacas128_rs1val_walking_sgn: &zacas128_rs1val_walking_sgn
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'walking_ones("rs1_val", 128)': 0
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'walking_zeros("rs1_val", 128)': 0
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'alternate("rs1_val",128)': 0
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zacas128_rs2val_walking_sgn: &zacas128_rs2val_walking_sgn
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'walking_ones("rs2_val", 128)': 0
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'walking_zeros("rs2_val", 128)': 0
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'alternate("rs2_val",128)': 0
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zacas64_rs1val_walking_sgn: &zacas64_rs1val_walking_sgn
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'walking_ones("rs1_val", 64)': 0
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'walking_zeros("rs1_val", 64)': 0
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'alternate("rs1_val",64)': 0
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zacas64_rs2val_walking_sgn: &zacas64_rs2val_walking_sgn
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'walking_ones("rs2_val", 64)': 0
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'walking_zeros("rs2_val", 64)': 0
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'alternate("rs2_val",64)': 0

‎coverage/rv32zacas.cgf

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# cover group format file for Zacas extension
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amocas.w:
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config:
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- check ISA:=regex(.*Zacas.*)
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opcode:
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amocas.w: 0
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rs1:
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<<: *all_regs_mx0
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rs2:
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<<: *all_regs
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rd:
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<<: *all_regs
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op_comb:
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<<: *zacas_op_comb
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val_comb:
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<<: [*base_rs1val_sgn, *base_rs2val_sgn]
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abstract_comb:
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<<: [*rs1val_walking, *rs2val_walking]
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amocas.d_32:
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config:
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- check ISA:=regex(.*Zacas.*)
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opcode:
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amocas.d_32: 0
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rs1:
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<<: *all_regs_mx0
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rs2:
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<<: *pair_regs
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rd:
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<<: *pair_regs
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op_comb:
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<<: *zacas_op_comb
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val_comb:
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<<: [*zacas_dcas_rs1val_sgn, *zacas_dcas_rs2val_sgn, *rfmt_val_comb_sgn]
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abstract_comb:
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<<: [*zacas64_rs1val_walking_sgn, *zacas64_rs2val_walking_sgn]

‎coverage/rv64zacas.cgf

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# cover group format file for Zacas extension
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amocas.w:
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config:
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- check ISA:=regex(.*Zacas.*)
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opcode:
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amocas.w: 0
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rs1:
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<<: *all_regs_mx0
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rs2:
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<<: *all_regs
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rd:
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<<: *all_regs
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op_comb:
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<<: *zacas_op_comb
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val_comb:
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<<: [*base_rs1val_sgn, *base_rs2val_sgn]
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abstract_comb:
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<<: [*rs1val_walking, *rs2val_walking]
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amocas.d_64:
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config:
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- check ISA:=regex(.*Zacas.*)
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opcode:
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amocas.d_64: 0
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rs1:
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<<: *all_regs_mx0
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rs2:
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<<: *all_regs
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rd:
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<<: *all_regs
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op_comb:
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<<: *zacas_op_comb
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val_comb:
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<<: [*base_rs1val_sgn, *base_rs2val_sgn, *rfmt_val_comb_sgn]
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abstract_comb:
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<<: [*rs1val_walking, *rs2val_walking]
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amocas.q:
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config:
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- check ISA:=regex(.*Zacas.*)
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opcode:
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amocas.q: 0
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rs1:
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<<: *all_regs_mx0
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rs2:
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<<: *pair_regs
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rd:
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<<: *pair_regs
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op_comb:
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<<: *zacas_op_comb
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val_comb:
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<<: [*zacas_dcas_rs1val_sgn, *zacas_dcas_rs2val_sgn, *rfmt_val_comb_sgn]
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abstract_comb:
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<<: [*zacas128_rs1val_walking_sgn, *zacas128_rs2val_walking_sgn]

‎riscv-test-suite/env/test_macros.h

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@@ -1099,6 +1099,56 @@ ADDI(swreg, swreg, RVMODEL_CBZ_BLOCKSIZE)
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sub x1,x1,tempreg ;\
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RVTEST_SIGUPD(swreg,x1,offset)
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// for updating signatures of Zacas paired destination register (RV32/RV64).
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#define RVTEST_SIGUPD_PZACAS(_BR,_R1,_R2,...) ;\
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.if NARG(__VA_ARGS__) == 1 ;\
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.set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0)) ;\
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.endif ;\
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.if (offset & (REGWIDTH-1)) != 0 ;\
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.warning "Signature Incorrect Offset Alignment." ;\
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.set offset, offset&(SIGALIGN-1)+SIGALIGN ;\
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.endif ;\
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CHK_OFFSET(_BR,REGWIDTH,0) ;\
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SREG _R1,offset(_BR) ;\
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CHK_OFFSET(_BR,REGWIDTH,1) ;\
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SREG _R2,offset(_BR) ;\
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.set offset,offset+(REGWIDTH)
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// Tests for a AMOCAS where operation width is <= xlen
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// First store a value that will cause a mismatch on cas
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// Test a failing amocas followed by a successful amocas
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#define TEST_CAS_OP(inst, rd, rs1, rs2, swap_val, sigptr, offset) \
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LI(rd, swap_val);\
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neg rd, rd;\
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LA(rs1, rvtest_data);\
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SREG rd, (rs1);\
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LI(rd, swap_val);\
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LI(rs2, swap_val);\
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LA(rs1, rvtest_data);\
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inst rd, rs2, (rs1);\
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inst rd, rs2, (rs1);\
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RVTEST_SIGUPD(sigptr,rd,offset);
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1132+
// Tests for a AMOCAS where operation width is <= xlen
1133+
// First store a value that will cause a mismatch on cas
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// Test a failing amocas followed by a successful amocas
1135+
#define TEST_DCAS_OP(inst, rd, rd_hi, rs1, rs2, rs2_hi, swap_val, swap_val_hi, sigptr, offset) \
1136+
LA(rs1, rvtest_data);\
1137+
LI(rd, swap_val);\
1138+
neg rd, rd;\
1139+
SREG rd, (rs1);\
1140+
LI(rd, swap_val_hi);\
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neg rd, rd;\
1142+
SREG rd, (__riscv_xlen/8)(rs1);\
1143+
LI(rd, swap_val);\
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LI(rd_hi, swap_val_hi);\
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LI(rs2, swap_val);\
1146+
LI(rs2_hi, swap_val_hi);\
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LA(rs1, rvtest_data);\
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inst rd, rs2, (rs1);\
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LA(rs1, rvtest_data);\
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inst rd, rs2, (rs1);\
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RVTEST_SIGUPD_PZACAS(sigptr,rd,rd_hi,offset);
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11031153
//--------------------------------- Migration aliases ------------------------------------------
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#ifdef RV_COMPLIANCE_RV32M

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