target/riscv: improve error messaging in case sbasize is zero
#1274
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From: Sriram Shanmuga <sriramharshalee@gmail.com> RISC-V Debug Specification v1.0 [3.14.22. System Bus Access Control and Status (`sbcs`, at 0x38)] states in `sbasize` field description: > Width of system bus addresses in bits. (0 indicates there is no bus access support.) Before the patch, the error message did not include the information about `sbcs.sbasize` being zero wich made it quite undescriptive: ``` [riscv.cpu] Turning off memory sampling because it failed. ``` Fixes riscv-collab#1270 Change-Id: I5402dd57dc9a81f65ee4c67d24e11c366006427c Signed-off-by: Sriram Shanmuga <sriramharshalee@gmail.com> Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
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@RaamyPi, please take a look |
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Looks good, thank you! |
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From: Sriram Shanmuga sriramharshalee@gmail.com
RISC-V Debug Specification v1.0 [3.14.22. System Bus Access Control and Status (
sbcs, at 0x38)] states insbasizefield description:Before the patch, the error message did not include the information about
sbcs.sbasizebeing zero wich made it quite undescriptive:Fixes #1270
Change-Id: I5402dd57dc9a81f65ee4c67d24e11c366006427c