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target/riscv: fix address translation in hypervisor mode #1258

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2 changes: 1 addition & 1 deletion .github/workflows/linux-build.yml
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ name: Linux Build
jobs:
# 32-bit, clang
build32:
runs-on: ubuntu-20.04
runs-on: ubuntu-latest
env:
CFLAGS: -m32
CC: clang
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23 changes: 4 additions & 19 deletions src/target/riscv/riscv.c
Original file line number Diff line number Diff line change
Expand Up @@ -3035,31 +3035,16 @@ static int riscv_mmu(struct target *target, int *enabled)
unsigned int xlen = riscv_xlen(target);

if (v_mode) {
/* vsatp and hgatp registers are considered active for the
* purposes of the address-translation algorithm unless the
* effective privilege mode is U and hstatus.HU=0. */
if (effective_mode == PRV_U) {
riscv_reg_t hstatus;
if (riscv_reg_get(target, &hstatus, GDB_REGNO_HSTATUS) != ERROR_OK) {
LOG_TARGET_ERROR(target, "Failed to read hstatus register.");
return ERROR_FAIL;
}

if (get_field(hstatus, HSTATUS_HU) == 0)
/* In hypervisor mode regular satp translation
* doesn't happen. */
return ERROR_OK;

}

/* In VU or VS mode, MMU is considered enabled when
* either hgatp or vsatp mode is not OFF */
riscv_reg_t vsatp;
if (riscv_reg_get(target, &vsatp, GDB_REGNO_VSATP) != ERROR_OK) {
LOG_TARGET_ERROR(target, "Failed to read vsatp register; priv=0x%" PRIx64,
priv);
return ERROR_FAIL;
}
/* vsatp is identical to satp, so we can use the satp macros. */
if (RISCV_SATP_MODE(xlen) != SATP_MODE_OFF) {
if (get_field(vsatp, RISCV_SATP_MODE(xlen)) != SATP_MODE_OFF) {
LOG_TARGET_DEBUG(target, "VS-stage translation is enabled.");
*enabled = 1;
return ERROR_OK;
Expand All @@ -3071,7 +3056,7 @@ static int riscv_mmu(struct target *target, int *enabled)
priv);
return ERROR_FAIL;
}
if (RISCV_HGATP_MODE(xlen) != HGATP_MODE_OFF) {
if (get_field(hgatp, RISCV_HGATP_MODE(xlen)) != HGATP_MODE_OFF) {
LOG_TARGET_DEBUG(target, "G-stage address translation is enabled.");
*enabled = 1;
} else {
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