Late timings

48K models

The ULA emits the INT signal one T-state earlier if /RFSH is low during the T-state immediately preceding the one in which the INT signal would normally begin. This causes an unprefixed instruction of 4 T-states, or a prefixed instruction of 8 T-states, that ends 14,338 T-states before the first VRAM pixel, to be immediately followed by the INT response, which then starts 14,337 T-states before the first VRAM pixel.

The details of this behavior were uncovered by Marta Sevillano Mancilla (aka MartianGirl and TheMartian) in May 2025. Weiv supposedly emulated this behavior some time earlier, but never shared an explanation of how it worked with the community.

Please note that the interaction between the /RFSH line of the Z80 CPU and the ULA may not be the cause of this behavior, but it serves to describe the conditions under which late timings occur on 48K models. Additionally, this behavior is temperature-dependent: some machines tend to exhibit late timings when cold and shift to early timings as they warm up.

+128K and +2 models

The ULA emits the INT signal one T-state earlier. This is common on ZX Spectrum +2 (grey) models. ZX Spectrum +128K (toastrack) models can also exhibit this behavior occasionally, possibly due to temperature.