|
350 | 350 | brcm,dma-channel-mask = <0x0fc0>;
|
351 | 351 | };
|
352 | 352 |
|
353 |
| - // Single-lane Gen3 PCIe |
354 |
| - // Outbound window at 0x14_000000-0x17_ffffff |
355 |
| - pcie0: pcie@100000 { |
356 |
| - compatible = "brcm,bcm2712-pcie"; |
357 |
| - reg = <0x10 0x00100000 0x0 0x9310>; |
358 |
| - device_type = "pci"; |
359 |
| - max-link-speed = <2>; |
360 |
| - #address-cells = <3>; |
361 |
| - #interrupt-cells = <1>; |
362 |
| - #size-cells = <2>; |
363 |
| - /* |
364 |
| - * Unused interrupts: |
365 |
| - * 208: AER |
366 |
| - * 215: NMI |
367 |
| - * 216: PME |
368 |
| - */ |
369 |
| - interrupt-parent = <&gicv2>; |
370 |
| - interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, |
371 |
| - <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; |
372 |
| - interrupt-names = "pcie", "msi"; |
373 |
| - interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
374 |
| - interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 |
375 |
| - IRQ_TYPE_LEVEL_HIGH>, |
376 |
| - <0 0 0 2 &gicv2 GIC_SPI 210 |
377 |
| - IRQ_TYPE_LEVEL_HIGH>, |
378 |
| - <0 0 0 3 &gicv2 GIC_SPI 211 |
379 |
| - IRQ_TYPE_LEVEL_HIGH>, |
380 |
| - <0 0 0 4 &gicv2 GIC_SPI 212 |
381 |
| - IRQ_TYPE_LEVEL_HIGH>; |
382 |
| - resets = <&bcm_reset 5>, <&bcm_reset 42>, <&pcie_rescal>; |
383 |
| - reset-names = "swinit", "bridge", "rescal"; |
384 |
| - msi-controller; |
385 |
| - msi-parent = <&pcie0>; |
386 |
| - |
387 |
| - ranges = <0x02000000 0x00 0x00000000 |
388 |
| - 0x17 0x00000000 |
389 |
| - 0x0 0xfffffffc>, |
390 |
| - <0x43000000 0x04 0x00000000 |
391 |
| - 0x14 0x00000000 |
392 |
| - 0x3 0x00000000>; |
393 |
| - |
394 |
| - dma-ranges = <0x43000000 0x10 0x00000000 |
395 |
| - 0x00 0x00000000 |
396 |
| - 0x10 0x00000000>; |
397 |
| - |
398 |
| - status = "disabled"; |
399 |
| - }; |
400 |
| - |
401 |
| - // Single-lane Gen3 PCIe |
402 |
| - // Outbound window at 0x18_000000-0x1b_ffffff |
403 |
| - pcie1: pcie@110000 { |
404 |
| - compatible = "brcm,bcm2712-pcie"; |
405 |
| - reg = <0x10 0x00110000 0x0 0x9310>; |
406 |
| - device_type = "pci"; |
407 |
| - max-link-speed = <2>; |
408 |
| - #address-cells = <3>; |
409 |
| - #interrupt-cells = <1>; |
410 |
| - #size-cells = <2>; |
411 |
| - /* |
412 |
| - * Unused interrupts: |
413 |
| - * 218: AER |
414 |
| - * 225: NMI |
415 |
| - * 226: PME |
416 |
| - */ |
417 |
| - interrupt-parent = <&gicv2>; |
418 |
| - interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, |
419 |
| - <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; |
420 |
| - interrupt-names = "pcie", "msi"; |
421 |
| - interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
422 |
| - interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 |
423 |
| - IRQ_TYPE_LEVEL_HIGH>, |
424 |
| - <0 0 0 2 &gicv2 GIC_SPI 220 |
425 |
| - IRQ_TYPE_LEVEL_HIGH>, |
426 |
| - <0 0 0 3 &gicv2 GIC_SPI 221 |
427 |
| - IRQ_TYPE_LEVEL_HIGH>, |
428 |
| - <0 0 0 4 &gicv2 GIC_SPI 222 |
429 |
| - IRQ_TYPE_LEVEL_HIGH>; |
430 |
| - resets = <&bcm_reset 7>, <&bcm_reset 43>, <&pcie_rescal>; |
431 |
| - reset-names = "swinit", "bridge", "rescal"; |
432 |
| - msi-controller; |
433 |
| - msi-parent = <&mip1>; |
434 |
| - |
435 |
| - // 2GB, 32-bit, non-prefetchable at PCIe 00_80000000 |
436 |
| - ranges = <0x02000000 0x00 0x80000000 |
437 |
| - 0x1b 0x80000000 |
438 |
| - 0x00 0x80000000>, |
439 |
| - // 14GB, 64-bit, prefetchable at PCIe 04_00000000 |
440 |
| - <0x43000000 0x04 0x00000000 |
441 |
| - 0x18 0x00000000 |
442 |
| - 0x03 0x80000000>; |
443 |
| - |
444 |
| - dma-ranges = <0x03000000 0x10 0x00000000 |
445 |
| - 0x00 0x00000000 |
446 |
| - 0x10 0x00000000>; |
447 |
| - |
448 |
| - status = "disabled"; |
449 |
| - }; |
450 |
| - |
451 |
| - pcie_rescal: reset-controller@119500 { |
452 |
| - compatible = "brcm,bcm7216-pcie-sata-rescal"; |
453 |
| - reg = <0x10 0x00119500 0x0 0x10>; |
454 |
| - #reset-cells = <0>; |
455 |
| - }; |
456 |
| - |
457 |
| - // Quad-lane Gen3 PCIe |
458 |
| - // Outbound window at 0x1c_000000-0x1f_ffffff |
459 |
| - pcie2: pcie@120000 { |
460 |
| - compatible = "brcm,bcm2712-pcie"; |
461 |
| - reg = <0x10 0x00120000 0x0 0x9310>; |
462 |
| - device_type = "pci"; |
463 |
| - max-link-speed = <2>; |
464 |
| - #address-cells = <3>; |
465 |
| - #interrupt-cells = <1>; |
466 |
| - #size-cells = <2>; |
467 |
| - /* |
468 |
| - * Unused interrupts: |
469 |
| - * 228: AER |
470 |
| - * 235: NMI |
471 |
| - * 236: PME |
472 |
| - */ |
473 |
| - interrupt-parent = <&gicv2>; |
474 |
| - interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>, |
475 |
| - <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; |
476 |
| - interrupt-names = "pcie", "msi"; |
477 |
| - interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
478 |
| - interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229 |
479 |
| - IRQ_TYPE_LEVEL_HIGH>, |
480 |
| - <0 0 0 2 &gicv2 GIC_SPI 230 |
481 |
| - IRQ_TYPE_LEVEL_HIGH>, |
482 |
| - <0 0 0 3 &gicv2 GIC_SPI 231 |
483 |
| - IRQ_TYPE_LEVEL_HIGH>, |
484 |
| - <0 0 0 4 &gicv2 GIC_SPI 232 |
485 |
| - IRQ_TYPE_LEVEL_HIGH>; |
486 |
| - resets = <&bcm_reset 32>, <&bcm_reset 44>, <&pcie_rescal>; |
487 |
| - reset-names = "swinit", "bridge", "rescal"; |
488 |
| - msi-controller; |
489 |
| - msi-parent = <&mip0>; |
490 |
| - |
491 |
| - // ~4GB, 32-bit, not-prefetchable at PCIe 00_00000000 |
492 |
| - ranges = <0x02000000 0x00 0x00000000 |
493 |
| - 0x1f 0x00000000 |
494 |
| - 0x0 0xfffffffc>, |
495 |
| - // 12GB, 64-bit, prefetchable at PCIe 04_00000000 |
496 |
| - <0x43000000 0x04 0x00000000 |
497 |
| - 0x1c 0x00000000 |
498 |
| - 0x03 0x00000000>; |
499 |
| - |
500 |
| - // 64GB system RAM space at PCIe 10_00000000 |
501 |
| - dma-ranges = <0x02000000 0x00 0x00000000 |
502 |
| - 0x1f 0x00000000 |
503 |
| - 0x00 0x00400000>, |
504 |
| - <0x43000000 0x10 0x00000000 |
505 |
| - 0x00 0x00000000 |
506 |
| - 0x10 0x00000000>; |
507 |
| - |
508 |
| - status = "disabled"; |
509 |
| - }; |
510 |
| - |
511 |
| - mip0: msi-controller@130000 { |
512 |
| - compatible = "brcm,bcm2712-mip-intc"; |
513 |
| - reg = <0x10 0x00130000 0x0 0xc0>; |
514 |
| - msi-controller; |
515 |
| - interrupt-controller; |
516 |
| - #interrupt-cells = <2>; |
517 |
| - brcm,msi-base-spi = <128>; |
518 |
| - brcm,msi-num-spis = <64>; |
519 |
| - brcm,msi-offset = <0>; |
520 |
| - brcm,msi-pci-addr = <0xff 0xfffff000>; |
521 |
| - }; |
522 |
| - |
523 |
| - mip1: msi-controller@131000 { |
524 |
| - compatible = "brcm,bcm2712-mip-intc"; |
525 |
| - reg = <0x10 0x00131000 0x0 0xc0>; |
526 |
| - msi-controller; |
527 |
| - interrupt-controller; |
528 |
| - #interrupt-cells = <2>; |
529 |
| - brcm,msi-base-spi = <247>; |
530 |
| - /* Actually 20 total, but the others are |
531 |
| - * both sparse and non-consecutive */ |
532 |
| - brcm,msi-num-spis = <8>; |
533 |
| - brcm,msi-offset = <8>; |
534 |
| - brcm,msi-pci-addr = <0xff 0xffffe000>; |
535 |
| - }; |
536 |
| - |
537 | 353 | syscon_piarbctl: syscon@400018 {
|
538 | 354 | compatible = "brcm,syscon-piarbctl", "syscon", "simple-mfd";
|
539 | 355 | reg = <0x10 0x00400018 0x0 0x18>;
|
|
590 | 406 | status = "disabled";
|
591 | 407 | };
|
592 | 408 |
|
593 |
| - bcm_reset: reset-controller@1504318 { |
594 |
| - compatible = "brcm,brcmstb-reset"; |
595 |
| - reg = <0x10 0x01504318 0x0 0x30>; |
596 |
| - #reset-cells = <1>; |
597 |
| - }; |
598 |
| - |
599 | 409 | v3d: v3d@2000000 {
|
600 | 410 | compatible = "brcm,2712-v3d";
|
601 | 411 | reg = <0x10 0x02000000 0x0 0x4000>,
|
|
0 commit comments