DT: bcm2711/bcm2712: use upstream property for controlling pcie clkreq

L1 sub-state support and clkreq control are intermingled in the hardware,
and upstream now have a tri-state property to control this. The default
behaviour is now to enable clkreq control if the property is absent.

Default Pi 5 PCIex1 to "safe" to avoid breaking expansion boards without
the CLKREQ# line connected. Make this explicit in the pciex1-compat-pi5
overlay, and remove the obsolete CM4 property.

Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>

Author: P33M

arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4.dts

@@ -422,10 +422,6 @@
 // =============================================
 // Board specific stuff here
 
-&pcie0 {
-       brcm,enable-l1ss;
-};
-
 &sdhost {
 	status = "disabled";
 };

arch/arm/boot/dts/overlays/README

@@ -3706,7 +3706,9 @@ Params: <None>
 Name:   pciex1-compat-pi5
 Info:   Compatibility features for pciex1 on Pi 5.
 Load:   dtoverlay=pciex1-compat-pi5,<param>=<val>
-Params: l1ss                    Enable ASPM L1 sub-state support
+Params: l1ss                    Enable RC ASPM L1 sub-state support. Requires
+                                that the CLKREQ# pin is connected to the
+                                endpoint.
         no-l0s                  Disable ASPM L0s
         no-mip                  Revert to the MSI target in the RC, instead of
                                 the MSI-MIP peripheral. Use if a) more than 8

arch/arm/boot/dts/overlays/pciex1-compat-pi5-overlay.dts

@@ -12,7 +12,7 @@
 	fragment@0 {
 		target = <&pciex1>;
 		__dormant__ {
-			brcm,enable-l1ss;
+			brcm,clkreq-mode = "default";
 		};
 	};
 

arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts

@@ -762,6 +762,7 @@ spi10_cs_pins: &spi10_cs_gpio1 {};
 
 &pcie1 {
 	status = "okay";
+	brcm,clkreq-mode = "safe";
 };
 
 &pcie2 {