Simple Assembler Simulator

Project Overview

This project involves designing and implementing a custom assembler and simulator for a 16-bit Instruction Set Architecture (ISA), undertaken by groups of three students. The ISA features a comprehensive set of instructions, encompassing arithmetic operations, data movement, and control flow, to facilitate a wide range of computational tasks.

The assembler translates assembly language instructions into machine code, with rigorous error checking against syntax and logical errors. It handles labels, variables, and ensures adherence to the ISA's specifications, including the proper use of registers, immediate values, and memory addresses.

The simulator executes the binary code generated by the assembler, simulating the specified behaviors of the ISA. It provides insights into the program's execution by simulating the effects on memory, registers, and the FLAGS register.

The project extends to support simple floating-point arithmetic and includes bonus challenges for memory access trace visualization and enhanced memory organization, offering a deeper dive into computer organization principles.

ISA Description

The ISA for this project is a 16-bit architecture supporting various instructions across six encoding types. It features arithmetic operations, data movement, control flow changes, and special operations.

• Registers: Seven general-purpose registers (R0-R6) and a FLAGS register.
• Memory: 8-bit address space, totaling 512 bytes.

Registers

• 7 General Purpose Registers: R0 to R6
• 1 FLAGS Register

Address Space

• 8-bit addressable, leading to a total space of 512 bytes.

Instruction Details

Arithmetic Operations

• add, sub, mul, div: Perform arithmetic operations on register contents.

Data Movement

• mov: Transfer data between registers or from an immediate value to a register.

Control Flow

• jmp, jlt, jgt, je: Conditional and unconditional jumps based on flag conditions.

Special Operations

• hlt: Halts execution.

Opcodes, Instruction Semantics, and Syntax

Addition (10000)

• Syntax: add reg1 reg2 reg3
• Semantics: Performs reg3 = reg1 + reg2. Sets overflow flag if necessary.

Subtraction (10001)

• Syntax: sub reg1 reg2 reg3
• Semantics: Performs reg3 = reg1 - reg2. Zeroes reg3 and sets overflow if reg2 > reg1.

Move Immediate (10010)

• Syntax: mov reg1 $Imm
• Semantics: Loads immediate value $Imm into reg1.

Move Register (10011)

• Syntax: mov reg1 reg2
• Semantics: Transfers the contents of reg1 to reg2.

Load (10100) and Store (10101)

• Syntax: ld reg1 mem_addr, st reg1 mem_addr
• Semantics: Load or store data between a register and a memory address.

Multiply (10110)

• Syntax: mul reg1 reg2 reg3
• Semantics: reg3 = reg1 * reg2. Sets overflow flag if necessary.

Divide (10111)

• Syntax: div reg1 reg2
• Semantics: Divides reg1 by reg2, storing the quotient and remainder in specified registers.

Logical Operations

• Includes xor, or, and, each performing bitwise operations on registers.

Shift and Rotate

• rs, ls: Shifts register contents right or left by an immediate value.

Compare (11110)

• Syntax: cmp reg1 reg2
• Semantics: Compares reg1 and reg2, updating FLAGS accordingly.

Jump Instructions

• Conditional jumps (jlt, jgt, je) based on FLAGS.

Halt (01010)

• Syntax: hlt
• Semantics: Halts execution.

Instruction Details

Instructions include:

1. Arithmetic Operations: add, sub, mul, div
2. Data Movement: mov
3. Control Flow: jmp, jlt, jgt, je
4. Special Operations: hlt

Encoding Types

• Type A: 3 register operations (e.g., add reg1 reg2 reg3)
• Type B: register and immediate operations (e.g., mov reg1 $Imm)
• Type C: 2 register operations (e.g., mov reg1 reg2)
• Type D & E: memory operations (e.g., ld reg1 mem_addr, st reg1 mem_addr)
• Type F: halt (e.g., hlt)

Floating-Point Arithmetic Extension

Support for floating-point operations in an 8-bit format is included, enhancing the assembler and simulator's capabilities.