|
1 | | -flowscripts contains minor and major scripts for: |
2 | | -fabric generation: core tasks and assisting tasks; |
3 | | -LVSDIE: compare routing graph against fabric Verilog; |
4 | | -BITGEN: from VPR inputs/outputs generate bitstream; |
5 | | -LVSBIT: compare VPR inputs/outputs against bitstream; |
6 | | -and many related tasks. |
| 1 | +sched.py |
| 2 | + - pull runtimes out of raptor.log + *.script, create scripts to balance jobs across multiple slots all running raptor_pin_vgl.sh |
| 3 | + |
| 4 | +raptor_pin_vgl.sh |
| 5 | + - modify bit_sim.sh to run raptor, run repin.py to improve pin locations, and run rerunvpr.sh to (re-)run VPR and/or validation. |
| 6 | + |
| 7 | +repin.py |
| 8 | + - read an old placement and create a new _pin_loc.place file with improved pin locations. |
| 9 | + |
| 10 | +rerunvpr.sh |
| 11 | + - depending on flag argument, re-run VPR pack/place/route/analysis, route2repack.py, bitgen.py, and lvsbit.py |
| 12 | + |
| 13 | +route2repack.py |
| 14 | + - read .route from VPR and update clock assignments in <design>_repack_constrains.xml needed by bitgen/OpenFPGA/... |
| 15 | + |
| 16 | +bitgen.py |
| 17 | + - read MANY files produced by synthesis and VPR and generate bitstreams for FPGA arrays. |
| 18 | + - can also (partially) analyze bitstream differences and create Verilog source for routing blocks. |
| 19 | + |
| 20 | +cbmapping.py |
| 21 | +cbmapping.tcl |
| 22 | + - create config bit mapping from array Verilog to support .bit format in bitgen. former uses vwalk, latter uses StarVision. |
| 23 | + |
| 24 | +lvsbit.py |
| 25 | + - read basenets (all nets, muxes, and .subckt/leaf pb_types) and bitstream, convert to netlist, and compare using gemini. |
| 26 | +cbpath.py |
| 27 | + - (debug) load basenets and settings into networkx, try to find paths |
| 28 | + |
| 29 | +basenets.py |
| 30 | +basenets.tcl |
| 31 | + - create basenets (all nets, muxes, and .subckt/leaf pb_types) from array Verilog to support lvsbit. former uses vwalk, latter uses StarVision. |
| 32 | + |
| 33 | +vwalk.py |
| 34 | + - Verilog reader and enumerator |
| 35 | + |
| 36 | +pack_dm.py |
| 37 | + - parser for VPR .net files |
| 38 | +arch_lib/ |
| 39 | + - parser for vpr.xml and openfpga.xml files. |
| 40 | +arch_etc/ |
| 41 | + - untested schemas for arch_lib |
| 42 | +analyze_vpr_hierarchies.py |
| 43 | + - sample client |
| 44 | +dump_vpr_xml.py |
| 45 | + - sample client |
| 46 | +dump_arch_xml.py |
| 47 | + - sample client |
| 48 | + |
| 49 | +lvsdie.py |
| 50 | + - read routing graph, read basenets, produce letter maps of unique routing tiles as an array check |
| 51 | + |
| 52 | +runs2vars.py |
| 53 | + - pull out VPR command arguments across many raptor.log files, make vars.sh files |
| 54 | + |
| 55 | +pv.py |
| 56 | + - "Python Verilog": support module for producing structural Verilog modules instantiating and connecting others. |
| 57 | + |
| 58 | +uf.py |
| 59 | + - UNION-FIND implementation |
| 60 | + |
| 61 | +xml2map.py |
| 62 | + - produce a generic csv config bit map file (for bitgen.py) from an XML bitstream |
| 63 | +xml2csv.sh |
| 64 | + - convert verbose OpenFPGA bitstream XML into compact csv for bitgen.py regressions |
| 65 | +genxyf.py |
| 66 | + - produce diagnostic files for bitgen.py debug |
| 67 | +vprwords.py |
| 68 | + - detect/present bad words/bits in bitgen.py output |
| 69 | +cats.sh |
| 70 | + - pull out categories of bits |
| 71 | +lutdiff.sh |
| 72 | + - extract/compare LUT contents from golden vs experimental |
| 73 | +vprfindnets.py |
| 74 | + - find misrouted nets using .csv and other files |
| 75 | +vprfindluts.py |
| 76 | + - find misfilled LUTs using .csv and other files |
| 77 | +cdiff.py |
| 78 | + - compare sorted bitstream files |
| 79 | +gb.sh |
| 80 | + - obsolete developmental/regression driver for bitgen.py |
| 81 | + |
| 82 | +*.mux *.json |
| 83 | + - very rough first-cut tile-level routing patterns from FPGA2024 paper |
| 84 | +genb.py |
| 85 | +genl.py |
| 86 | + - scripts to produce them |
| 87 | +mux2stat.py |
| 88 | + - produce stat table for .mux file |
| 89 | +lr2mux.py |
| 90 | + - obsolete LUTRAM experiment |
| 91 | +fgraph.py |
| 92 | + - compute max flow through CB/LR as sanity check |
| 93 | + |
| 94 | +stamp.py |
| 95 | + - read old graph, read *.mux, stamp copies throughout, write out again |
| 96 | +loop.py |
| 97 | + - obsolete/incomplete/experimental: looping attempt from FPGA2024 paper |
| 98 | +make_stamped_graph.sh |
| 99 | + - obsolete wrapper/driver for stamp.py |
| 100 | +make_rb.sh |
| 101 | + - obsolete wrapper/driver for bitgen.py's routing tile writing function |
| 102 | + |
| 103 | +rrpath.py |
| 104 | + - load a routing graph into networkx and look for paths between nodes |
| 105 | + |
| 106 | +rrgvgsb.py |
| 107 | +rrgvgsb |
| 108 | + - obsolete/incomplete/experimental: compare routing graph to OpenFPGA GSBs + wrapper |
| 109 | + |
| 110 | +genfab.sh |
| 111 | + - NEW BUILD: bash wrapper to run OpenFPGA directly. we use only sub_module/ and lb/. |
| 112 | +tiles.py |
| 113 | + - NEW BUILD: produce array tiles from lb/ and /route made by bitgen.py special function. |
| 114 | +fpga_top.py |
| 115 | + - NEW BUILD: produce array top-level |
| 116 | +genmuxmem.py |
| 117 | + - NEW BUILD: augment mux-defining file with new muxes we referred to. |
| 118 | +reusetiles.py |
| 119 | + - NEW BUILD: in a large array, reuse tiles from a smaller arrray |
| 120 | +simreplace.sh |
| 121 | + - NEW BUILD: obsolete handling of fabric Verilog changes |
| 122 | + |
| 123 | +Makefile |
| 124 | + - OLD BUILD: stamp flow |
| 125 | +pgen |
| 126 | + - OLD BUILD: extensive StarVision script to fix OpenFPGA errors and deficiences, and add in stamped routing |
| 127 | +fixiotiles2 |
| 128 | + - OLD BUILD: follow-up smaller step to previous |
| 129 | +make_gemini_release_basenets.sh |
| 130 | + - OLD BUILD: make basenets.pin.gz |
| 131 | +make_gemini_release_cbmapping.sh |
| 132 | + - OLD BUILD: make cbmapping.csv.gz |
| 133 | + |
| 134 | +nodes |
| 135 | + - duplicate attributes and order of how VPR creates nodes (CHANX/Y) |
| 136 | + |
| 137 | +v2sel.py |
| 138 | + - figure out select signals in Verilog mux source |
| 139 | + |
| 140 | +pincanon.py |
| 141 | + - extract/canonicalize PIN/NET (basenets) files in various ways |
| 142 | + |
| 143 | +xml2json.py |
| 144 | + - old XML --> JSON formatting experiment |
| 145 | +p2x.py |
| 146 | + - old PYX --> XML experiment |
| 147 | +yml2csv.py |
| 148 | + - convert simple YAML to csv |
| 149 | + |
| 150 | +vparse.py |
| 151 | + - verilog parser module. never used. |
| 152 | + |
| 153 | +place_opt/ |
| 154 | + - incomplete experiment to reorder CLB contents to improve inter-tile routing |
| 155 | + |
| 156 | +ptbit/ |
| 157 | + - translate bitstreams into set_case_analysis commands and run PT/STA on a configured design |
| 158 | + |
| 159 | +muxopt/ |
| 160 | + - use Yosys to improve muxes used inside array Verilog |
| 161 | + |
| 162 | +evalroute/ |
| 163 | + - collect statistics from experiments for FPGA2024 paper |
| 164 | +evalroute/flute-3.1/ |
| 165 | + - FLUTE-3.1 Steiner tree library (copy) |
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