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lines changed- VERSION.md+1-1
- openfpga/src/annotation/route_clock_rr_graph.cpp+55-10
- openfpga/src/base/openfpga_pb_pin_fixup.cpp+215-51
- openfpga/src/base/openfpga_pb_pin_fixup.h+1-1
- openfpga/src/base/openfpga_pb_pin_fixup_template.h+1-4
- openfpga/src/fpga_bitstream/build_routing_bitstream.cpp+9-3
- openfpga_flow/openfpga_shell_scripts/example_clkntwk_pb_pin_fixup_no_ace_script.openfpga+78
- openfpga_flow/regression_test_scripts/basic_reg_test.sh+3
- openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/clk_arch_1clk_1rst_2layer.xml+32
- openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_reset.xml+8
- openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_resetb.xml+8
- openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/repack_pin_constraints.xml+4
- openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/task.conf+54
- openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/clk_arch_1clk_1rst_2layer.xml+34
- openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/pin_constraints_clk.xml+8
- openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/pin_constraints_rst.xml+8
- openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/pin_constraints_rst_and_clk.xml+8
- openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/repack_pin_constraints.xml+4
- openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/task.conf+56
- openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/clk_arch_1clk_1rst_3layer.xml+72
- openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/pin_constraints_reset.xml+8
- openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/pin_constraints_resetb.xml+8
- openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/repack_pin_constraints.xml+4
- openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/task.conf+54
- openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm_ClkOnLeft.xml+642
- yosys+1-1
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