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15 repositories
vyges-ip-template
Public template🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation- VyBox Lite: One-click Codespaces environment for trying Vyges chip/IP development in your browser.
vyges-metadata-spec
Public📋 Vyges Metadata Specification - Standardized format for hardware IP discovery and integrationmlow-codec-ip
Publichilbert-transformer
PublicA fully pipelined digital Hilbert transformer IP block for DSP applications including single sideband modulation, amplitude/phase detection, and quadrature signal processing. Optimized for FPGA and ASIC implementations with configurable precision and maximum throughput.full-adder-ip
PublicA configurable full adder IP with three implementation approaches (simple XOR/AND, modular half adder, carry lookahead) following Vyges conventions. Includes comprehensive verification with SystemVerilog, UVM, and Cocotb testbenches supporting multiple simulators (Icarus, Verilator, Questa, VCS, Xcelium). Production-ready for ASIC/FPGA w/ 500MHz- Programmable ADC IP with Cadence PDK support, featuring behavioral models, comprehensive testbenches, and automated verification flows for mixed-signal design.
pwm-controller
Publicsd-card-controller-ip
Publicuart-controller
PublicA configurable UART controller IP with APB interface, FIFO support, and interrupt capabilities. Designed for SkyWater 130nm Open Source PDK with comprehensive verification and OpenLane integration.- Configurable, high-performance FFT hardware IP core for ASIC/FPGA. Pipelined radix-2 DIF, 256–4096-point support, 16-bit fixed-point, double-buffered memory, APB/AXI interfaces. Optimized for throughput and low latency.
.github
Publicvyges
Publiccommunity
Public🏗️ Central hub for Vyges community discussions, issues, feature requests, and collaboration