Repositories list

• svaunit

  Public
  SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)

  SystemVerilog

  •

  Other

  •22•0•0•0•Updated May 30, 2025May 30, 2025

• i2c_avip

  Public
  I2C Accelerated VIP

  SystemVerilog

  •6•14•1•0•Updated Dec 26, 2024Dec 26, 2024

• computerArchitectureCourse

  Public
  Assembly

  •0•2•0•0•Updated Feb 29, 2024Feb 29, 2024

• uvm_tb_arch_doc_py

  Public
  A python project to automatically generate the UVM testbench document.

  Python

  •28•20•11•3•Updated Feb 27, 2024Feb 27, 2024

• FPGABoard_edgeSpartan6

  Public
  This project aims at learning Digital Design and Verilog using FPGA board - Edge Spartan6

  Verilog

  •21•2•1•0•Updated Feb 20, 2024Feb 20, 2024

• verilogHDL

  Public
  Verilog

  •1•7•0•0•Updated Feb 14, 2024Feb 14, 2024

• collector

  Public
  Testing project

  Python

  •2•0•3•1•Updated Feb 8, 2024Feb 8, 2024

• verilator

  Public
  Verilator open-source SystemVerilog simulator and lint system

  C++

  •

  GNU Lesser General Public License v3.0

  •700•1•0•0•Updated Jan 5, 2024Jan 5, 2024

• SystemVerilogCourse

  Public
  This is a detailed SystemVerilog course

  SystemVerilog

  •51•0•0•0•Updated Jan 4, 2024Jan 4, 2024

• AXI_FIFO_BFM_2

  Public
  AXI4 with a FIFO integrated with VIP

  SystemVerilog

  •84•0•0•0•Updated Jul 3, 2023Jul 3, 2023

• challenge2_designdefenders

  Public
  Lab infos

  Verilog

  •21•0•0•1•Updated May 2, 2023May 2, 2023

• edge_spartan6-5

  Public
  Lab infos

  Verilog

  •21•0•0•0•Updated May 2, 2023May 2, 2023

• edge_spartan6-6

  Public
  Lab infos

  Verilog

  •21•0•0•0•Updated May 2, 2023May 2, 2023

• Mbits_AXI4_AVIP-1

  Public
  Mbits axi4 avip

  SystemVerilog

  •

  MIT License

  •32•0•0•0•Updated Apr 17, 2023Apr 17, 2023

• Mbits_AXI4_AVIP

  Public
  Mbits axi4 avip

  SystemVerilog

  •

  MIT License

  •32•2•0•0•Updated Apr 17, 2023Apr 17, 2023

• edge_spartan6-4

  Public
  Lab infos

  Verilog

  •21•0•0•0•Updated Apr 10, 2023Apr 10, 2023

• edge_spartan6-3

  Public
  Lab infos

  Verilog

  •21•0•0•0•Updated Apr 10, 2023Apr 10, 2023

• edge_spartan6-2

  Public
  Lab infos

  Verilog

  •21•0•0•0•Updated Apr 10, 2023Apr 10, 2023

• edge_spartan6-1

  Public
  Lab infos

  Verilog

  •21•0•0•0•Updated Apr 10, 2023Apr 10, 2023

• axi4_avip

  Public
  Development of AXI4 Accelerated VIP

  SystemVerilog

  •12•31•2•0•Updated Apr 3, 2023Apr 3, 2023

• SystemVerilog_Course

  Public
  This is a detailed SystemVerilog course

  SystemVerilog

  •51•0•0•0•Updated Jan 29, 2023Jan 29, 2023

• apb_avip

  Public
  ABP Accelerated VIP

  SystemVerilog

  •12•22•3•0•Updated Jan 9, 2023Jan 9, 2023

• UVMF

  Public
  SystemVerilog

  •8•16•10•5•Updated Jan 7, 2023Jan 7, 2023

• linux_course

  Public
  This course walks you through the Linux OS commands and usage.

  Shell

  •7•19•0•0•Updated Sep 26, 2022Sep 26, 2022

• uart_avip

  Public
  UART Accelerated VIP

  3•13•1•0•Updated Aug 10, 2022Aug 10, 2022

• fuseSoc_avip_usage

  Public
  To learn and understand the fuseSoC project and use it to run the AVIP projects

  0•1•0•0•Updated Jul 12, 2022Jul 12, 2022

• spi_avip-1

  Public
  SPI protocol Accelerated VIP

  SystemVerilog

  •17•0•0•0•Updated Apr 21, 2022Apr 21, 2022

• spi_avip

  Public
  SPI protocol Accelerated VIP

  SystemVerilog

  •17•24•9•1•Updated Apr 21, 2022Apr 21, 2022

• pulpino__spi_master__ip_verification

  Public
  To verify the SPI Master IP using the APB and SPI AVIPs

  SystemVerilog

  •7•20•1•1•Updated Apr 21, 2022Apr 21, 2022

• pulpino__spi_master__subsystem_verification

  Public
  Verification of pulpino subsystem consisting of AXI input interface and SPI as output interface

  SystemVerilog

  •3•5•3•0•Updated Apr 21, 2022Apr 21, 2022