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Users following mbits-mirafra

@Karan-nevage
Karankumar Nevage Karan-nevage
Design Verification Fresher | Verilog, SystemVerilog & Python | UVM | AXI, AHB, APB | ASIC, SOC & RISC-V Enthusiast |

Fluxray Electronics Hormavu, Bengaluru East, Karnatak -560113

@rihan1228
mohammed rihan rihan1228
web developer A passionate learner exploring the exciting worlds of software and hardware.
@russelvernon
Russel vernon Gonsalves russelvernon
Embedded Systems Engineer|Verification Engineer|PCB Designer|Electronics & Communication Engineer
@BizzoB27
Bhawesh SB BizzoB27
🔬VLSI Design & Verification Engineer | RTL Design | SystemVerilog | UVM | AXI Protocol 💡Passionate about Digital Design, Testbenches, & Functional Verificatn
@nrllhclb
nrllhclb
Digital Design and Verification Engineer
@kanthimathi-2303
Kanthimathi kanthimathi-2303
Verification Engineer | Learning SystemVerilog & UVM 😊 Exploring testbenches, simulations, and RTL verification Love solving bugs and eager to learn🤩
@SudheerJanagama
Sudheer Anand SudheerJanagama
VLSI Frontend | Digital Design and Verification
@Vk140704
Vishalpalanisamy Vk140704
RTL Design and Verification Engineer at Silicon Craft VLSI|Verilog

Silicon Craft VLSI chennai

@ravisaanthosh
SANTHOSH R ravisaanthosh
Trust your own process it's make a time but trust it.............

silicic innova technologies pvt lmt VELLORE GUDIYATHAM

@opbajya
Op opbajya
M.tech at MNNIT Allahabad
@sudeepasundi
Sudeep Asundi sudeepasundi
VLSI SoC Design Trainee passionate about Verilog, digital design and analog design
@snevindsouza
Snevin Leoneel Dsouza snevindsouza

N.M.A.M Institute of Technology, Nitte Mangalore

@SrinikethSekar
Sriniketh Sekar SrinikethSekar
RTL Design and Verification Engineer at Silicon Craft VLSI|Verilog,System Verilog, UVM, Perl

HCLTech Chennai