🔬VLSI Design & Verification Engineer | RTL Design | SystemVerilog | UVM | AXI Protocol
💡Passionate about Digital Design, Testbenches, & Functional Verificatn
Popular repositories Loading
-
fundamentals-of-system-verilog
fundamentals-of-system-verilog Publicblocking and non-blocking
SystemVerilog
-
-
-
mux_3x1
mux_3x1 PublicA simple 3-to-1 multiplexer (MUX) design that selects one of three input signals based on a 2-bit select line. Useful for digital logic, FPGA/ASIC design, and learning basic combinational circuits.
Verilog
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.