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    66 repositories

    • iopmp-spec

      Public
      This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate the accesses issued from the bus masters.
      C
      •
      Creative Commons Attribution 4.0 International
      •9•1•0•0•Updated Aug 15, 2025Aug 15, 2025

    • cva6

      Public
      The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
      Assembly
      •
      Other
      •822•2•0•1•Updated Aug 8, 2025Aug 8, 2025

    • riscv-ci-partners

      Public
      RISC-V CI Partners Project
      HTML
      •
      MIT License
      •0•3•0•0•Updated Jul 31, 2025Jul 31, 2025

    • iree-fork-pack

      Public
      A retargetable MLIR-based machine learning compiler and runtime toolkit.
      C++
      •
      Apache License 2.0
      •743•0•0•0•Updated Jul 20, 2025Jul 20, 2025

    • Infinite-ISP_LinuxCameraStack

      Public
      Extending Linux support to enable Infinite-ISP on FPGA for the development of a libcamera-based camera application stack.
      linuxispfpga-soclibcameracamera-applicationlinux-driver-programming
      C++
      •
      Apache License 2.0
      •4•2•2•1•Updated Jul 12, 2025Jul 12, 2025

    • Infinite-ISP

      Public
      A camera ISP (image signal processor) pipeline that contains modules with simple to complex algorithms implemented at the application level.
      computer-visionimage-processingispimage-signal-processorcamera-pipeline
      Python
      •
      Apache License 2.0
      •61•239•16•1•Updated Jul 1, 2025Jul 1, 2025

    • iree-fork

      Public archive
      A retargetable MLIR-based machine learning compiler and runtime toolkit.
      C++
      •
      Apache License 2.0
      •743•0•0•0•Updated Jun 13, 2025Jun 13, 2025

    • MLIR

      Public
      MLIR Tutorial
      C++
      •2•2•0•0•Updated Jun 8, 2025Jun 8, 2025

    • basejump_stl_fork

      Public
      BaseJump STL: A Standard Template Library for SystemVerilog
      SystemVerilog
      •
      Other
      •108•0•0•0•Updated Jun 4, 2025Jun 4, 2025

    • aligner

      Public
      0•0•0•0•Updated May 21, 2025May 21, 2025

    • Infinite-ISP_ReferenceModel

      Public
      A Python based fixed-point implementation of the Infinite-ISP design for ASIC and FPGA design and verification.
      computer-visionimage-processingrtlispcamera-pipelineimage-signal-processing
      Python
      •
      Apache License 2.0
      •15•28•8•3•Updated May 13, 2025May 13, 2025

    • cvw

      Public
      CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
      SystemVerilog
      •
      Other
      •300•0•0•0•Updated Mar 13, 2025Mar 13, 2025

    • cvw-arch-verif

      Public
      The purpose of the repo is to support CORE-V Wally architectural verification
      SystemVerilog
      •
      Other
      •36•0•0•0•Updated Feb 14, 2025Feb 14, 2025

    • Infinite-ISP_FPGABinaries

      Public
      Infinite-ISP Image Signal Processing Pipeline FPGA Binaries for XCK26 Zynq® UltraScale+™ MPSoC present on Xilinx® Kria™ KV260 Vision AI Starter Kit and Efinix® Titanium Ti180 J484 Development Kit
      fpgaxilinxxilinx-fpgaxilinx-vivado
      Python
      •
      Apache License 2.0
      •5•11•0•1•Updated Dec 30, 2024Dec 30, 2024

    • Mojo-SIMD

      Public
      Mojo
      •0•0•0•0•Updated Dec 19, 2024Dec 19, 2024

    • matmul_kernel

      Public
      C
      •1•0•0•0•Updated Nov 18, 2024Nov 18, 2024

    • MoonDreamMojo

      Public
      Mojo
      •1•4•0•0•Updated Oct 31, 2024Oct 31, 2024

    • evsoc

      Public
      This repo is for Edge Vision SoC framework, which facilitates quick porting of users' design for Edge AI and Vision solutions.
      SystemVerilog
      •
      MIT License
      •12•2•0•0•Updated Oct 8, 2024Oct 8, 2024

    • MoonDreamMojoOld

      Public
      0•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • riscv-iommu

      Public
      IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
      SystemVerilog
      •
      Apache License 2.0
      •26•0•0•0•Updated Sep 30, 2024Sep 30, 2024

    • Llava

      Public
      Jupyter Notebook
      •1•0•0•0•Updated Sep 24, 2024Sep 24, 2024

    • clang-builtin-tutorial

      Public
      5•20•0•0•Updated Aug 28, 2024Aug 28, 2024

    • Infinite-ISP_TuningTool

      Public
      Infinite-ISP Tuning Tool is a console-based ISP (image signal processor) tuning application that is specifically designed to tune various modules in the Infinite-ISP_GM.
      computer-visionimage-processingispimage-signal-processortuning-toolcamera-pipelineisp-tuning-tool
      Python
      •
      Apache License 2.0
      •8•30•2•0•Updated Aug 26, 2024Aug 26, 2024

    • Infinite-ISP_Hardware

      Public
      Apache License 2.0
      •0•0•0•0•Updated Aug 26, 2024Aug 26, 2024

    • cvw-arch-functional-verif

      Public
      SystemVerilog
      •0•0•0•0•Updated Aug 6, 2024Aug 6, 2024

    • petalinux_kria

      Public
      C
      •
      Apache License 2.0
      •0•0•0•0•Updated Aug 2, 2024Aug 2, 2024

    • Mojo-Yolo

      Public
      Mojo
      •2•1•0•0•Updated Jul 24, 2024Jul 24, 2024

    • RISCV-10xE-DV-Hackathon

      Public
      Cohort-at-10x-Cores-VeeR-EH1
      SystemVerilog
      •
      Apache License 2.0
      •231•0•2•0•Updated Jul 1, 2024Jul 1, 2024

    • cv32e40p

      Public
      CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
      SystemVerilog
      •
      Other
      •463•0•0•0•Updated Jun 28, 2024Jun 28, 2024

    • core-v-verif

      Public
      Functional verification project for the CORE-V family of RISC-V cores.
      Assembly
      •
      Other
      •251•0•0•0•Updated Jun 27, 2024Jun 27, 2024