Merge branches 'clk-microchip', 'clk-samsung' and 'clk-qcom' into clk-next

* clk-microchip:
  clk, reset: microchip: mpfs: fix incorrect preprocessor conditions
  clock, reset: microchip: move all mpfs reset code to the reset subsystem

* clk-samsung:
  clk: samsung: Don't register clkdev lookup for the fixed rate clocks
  clk: samsung: gs101: drop unused HSI2 clock parent data
  clk: samsung: gs101: mark some apm UASC and XIU clocks critical
  clk: samsung: gs101: add support for cmu_hsi2
  clk: samsung: gs101: add support for cmu_hsi0
  dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit
  dt-bindings: clock: google,gs101-clock: add HSI0 clock management unit
  clk: samsung: gs101: propagate PERIC1 USI SPI clock rate
  clk: samsung: gs101: propagate PERIC0 USI SPI clock rate
  clk: samsung: exynosautov9: fix wrong pll clock id value
  dt-bindings: clock: samsung,s3c6400-clock: convert to DT Schema
  clk: samsung: exynos850: Add CMU_CPUCL0 and CMU_CPUCL1
  clk: samsung: Implement manual PLL control for ARM64 SoCs

* clk-qcom: (27 commits)
  clk: qcom: clk-alpha-pll: fix rate setting for Stromer PLLs
  clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018
  clk: qcom: Fix SM_GPUCC_8650 dependencies
  clk: qcom: Fix SC_CAMCC_8280XP dependencies
  clk: qcom: mmcc-msm8998: fix venus clock issue
  clk: qcom: dispcc-sm8650: fix DisplayPort clocks
  clk: qcom: dispcc-sm8550: fix DisplayPort clocks
  clk: qcom: dispcc-sm6350: fix DisplayPort clocks
  clk: qcom: dispcc-sm8450: fix DisplayPort clocks
  clk: qcom: clk-cbf-8996: use HUAYRA_APSS register map for cbf_pll
  clk: qcom: apss-ipq-pll: constify clk_init_data structures
  clk: qcom: apss-ipq-pll: constify match data structures
  clk: qcom: apss-ipq-pll: move Huayra register map to 'clk_alpha_pll_regs'
  clk: qcom: apss-ipq-pll: reuse Stromer reg offsets from 'clk_alpha_pll_regs'
  clk: qcom: apss-ipq-pll: use stromer ops for IPQ5018 to fix boot failure
  clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple conf
  clk: qcom: clk-rcg2: add support for rcg2 freq multi ops
  clk: qcom: clk-rcg: introduce support for multiple conf for same freq
  clk: qcom: hfpll: Add QCS404-specific compatible
  dt-bindings: clock: qcom,hfpll: Convert to YAML
  ...

Author: bebarino

Documentation/devicetree/bindings/clock/google,gs101-clock.yaml

@@ -30,16 +30,18 @@ properties:
       - google,gs101-cmu-top
       - google,gs101-cmu-apm
       - google,gs101-cmu-misc
+      - google,gs101-cmu-hsi0
+      - google,gs101-cmu-hsi2
       - google,gs101-cmu-peric0
       - google,gs101-cmu-peric1
 
   clocks:
     minItems: 1
-    maxItems: 3
+    maxItems: 5
 
   clock-names:
     minItems: 1
-    maxItems: 3
+    maxItems: 5
 
   "#clock-cells":
     const: 1
@@ -72,6 +74,55 @@ allOf:
           items:
             - const: oscclk
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: google,gs101-cmu-hsi0
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (24.576 MHz)
+            - description: HSI0 bus clock (from CMU_TOP)
+            - description: DPGTC (from CMU_TOP)
+            - description: USB DRD controller clock (from CMU_TOP)
+            - description: USB Display Port debug clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: bus
+            - const: dpgtc
+            - const: usb31drd
+            - const: usbdpdbg
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - google,gs101-cmu-hsi2
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (24.576 MHz)
+            - description: High Speed Interface bus clock (from CMU_TOP)
+            - description: High Speed Interface pcie clock (from CMU_TOP)
+            - description: High Speed Interface ufs clock (from CMU_TOP)
+            - description: High Speed Interface mmc clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: bus
+            - const: pcie
+            - const: ufs
+            - const: mmc
+
   - if:
       properties:
         compatible:

Documentation/devicetree/bindings/clock/qcom,hfpll.txt

@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,hfpll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm High-Frequency PLL
+
+maintainers:
+  - Bjorn Andersson <andersson@kernel.org>
+
+description:
+  The HFPLL is used as CPU PLL on various Qualcomm SoCs.
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - qcom,msm8974-hfpll
+          - qcom,msm8976-hfpll-a53
+          - qcom,msm8976-hfpll-a72
+          - qcom,msm8976-hfpll-cci
+          - qcom,qcs404-hfpll
+      - const: qcom,hfpll
+        deprecated: true
+
+  reg:
+    items:
+      - description: HFPLL registers
+      - description: Alias register region
+    minItems: 1
+
+  '#clock-cells':
+    const: 0
+
+  clocks:
+    items:
+      - description: board XO clock
+
+  clock-names:
+    items:
+      - const: xo
+
+  clock-output-names:
+    description:
+      Name of the PLL. Typically hfpllX where X is a CPU number starting at 0.
+      Otherwise hfpll_Y where Y is more specific such as "l2".
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+  - clocks
+  - clock-names
+  - clock-output-names
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@f908a000 {
+        compatible = "qcom,msm8974-hfpll";
+        reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
+        #clock-cells = <0>;
+        clock-output-names = "hfpll0";
+        clocks = <&xo_board>;
+        clock-names = "xo";
+    };

Documentation/devicetree/bindings/clock/qcom,hfpll.yaml

@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,s3c6400-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S3C6400 SoC clock controller
+
+maintainers:
+  - Krzysztof Kozlowski <krzk@kernel.org>
+
+description: |
+  There are several clocks that are generated outside the SoC. It is expected
+  that they are defined using standard clock bindings with following
+  clock-output-names and/or provided as clock inputs to this clock controller:
+   - "fin_pll" - PLL input clock (xtal/extclk) - required,
+   - "xusbxti" - USB xtal - required,
+   - "iiscdclk0" - I2S0 codec clock - optional,
+   - "iiscdclk1" - I2S1 codec clock - optional,
+   - "iiscdclk2" - I2S2 codec clock - optional,
+   - "pcmcdclk0" - PCM0 codec clock - optional,
+   - "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410.
+
+  All available clocks are defined as preprocessor macros in
+  include/dt-bindings/clock/samsung,s3c64xx-clock.h header.
+
+properties:
+  compatible:
+    enum:
+      - samsung,s3c6400-clock
+      - samsung,s3c6410-clock
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  "#clock-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@7e00f000 {
+        compatible = "samsung,s3c6410-clock";
+        reg = <0x7e00f000 0x1000>;
+        #clock-cells = <1>;
+        clocks = <&fin_pll>;
+    };