APB_2Slave

This repository contains the verification environment for the AMBA APB (Advanced Peripheral Bus) protocol. The APB protocol is designed for low-bandwidth, low-power peripherals like UART, Timers, GPIOs, etc.

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📘 Overview

This APB design includes:

• One APB master controlled via external signals
• Two APB slaves selected using the 9th bit of PADDR
• Transfer only occurs when TRANSFER = 1

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Architecture

APB Interface Block Diagram

Operation Of APB

APB Master-Slave Block Diagram

🔁 APB Signal Summary

Signal	Width	Source	Description
PCLK	1-bit	Clock Source	Clock input. All activity on rising edge.
PRESETn	1-bit	System Bus	Active-low reset.
PADDR	9-bit	APB Bridge	Address bus. Slave is selected via 9th bit.
PWDATA	8-bit	APB Bridge	Data to be written.
PRDATA	8-bit	Slave	Data to be read.
PWRITE	1-bit	APB Bridge	1 = Write, 0 = Read.
PSELx	1-bit	APB Bridge	Select line for each slave.
PENABLE	1-bit	APB Bridge	Indicates 2nd phase of data transfer.
PREADY	1-bit	Slave	Slave ready for transfer completion.
PSLVERR	1-bit	Slave	Indicates error on transfer.
TRANSFER	1-bit	System Bus	High = Enable APB operation.

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✅ Test Plan

Apb Test Cases

How to Run

Compile the testbench

vlog <top_file.sv>

Simulate and Run

vsim -c -do "run -all; exit;" <top_module name>