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1. Implementation-and-Formal-Correctness-of-a-Floating-Point-Adder Implementation-and-Formal-Correctness-of-a-Floating-Point-Adder Public

   A exercise on theorem proving, design and correctness of a floating point adder in ACL2

   Common Lisp 2

2. MUL-DIV-REM-verification-of-a-RV32IM-processor MUL-DIV-REM-verification-of-a-RV32IM-processor Public

   This repository contains project files of MUL/DIV/REM instruction verification for RISCV RV32IM sequential processor

   Verilog 2

3. FPGA-implementation-of-1D-convolution-filter- FPGA-implementation-of-1D-convolution-filter- Public

   VHDL 1

4. Formal-Equivalence-of-two-RISCV-processor Formal-Equivalence-of-two-RISCV-processor Public

   Architectural Equivalence between a sequential and a in-order pipelined RISCV processor using Formal Verification

   Verilog 1

5. reinforce-safe_exploration-gridworld reinforce-safe_exploration-gridworld Public

   Jupyter Notebook

6. verilog2dimacs verilog2dimacs Public

   Forked from jpsety/verilog2dimacs

   Coverts a generic Verilog netlist into the DIMACS format compatible with many SAT solvers

   Python