Xhci DMA buffer Allocation fix

[eeshanl]

Description

Changes Pool allocations to use the PciIo interface's AllocateBuffer routine

DMA buffers should be page aligned and always allocated with the appropriate PciIo interface.

On some platforms, where IoMmu is enabled it is possible that if two allocations occur within the same page, and one gets unmapped via PciIo->Unmap, it will also unmap the other allocated address.

• Impacts functionality?
• Impacts security?
• Breaking change?
• Includes tests?
• Includes documentation?

How This Was Tested

Tested on physical arm platform.

Integration Instructions

N/A

[codecov-commenter]

Codecov Report

❌ Patch coverage is 0% with 54 lines in your changes missing coverage. Please review.
⚠️ Please upload report for BASE (release/202502@c1cbe41). Learn more about missing BASE report.

Files with missing lines	Patch %	Lines
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c	0.00%	54 Missing ⚠️

Additional details and impacted files

@@                Coverage Diff                @@
##             release/202502    #1539   +/-   ##
=================================================
  Coverage                  ?    1.55%           
=================================================
  Files                     ?      636           
  Lines                     ?   233949           
  Branches                  ?      370           
=================================================
  Hits                      ?     3649           
  Misses                    ?   230287           
  Partials                  ?       13           

Flag	Coverage Δ
MdeModulePkg	1.55% <0.00%> (?)

Flags with carried forward coverage won't be shown. Click here to find out more.

☔ View full report in Codecov by Sentry.
📢 Have feedback on the report? Share it here.

🚀 New features to boost your workflow:

• ❄️ Test Analytics: Detect flaky tests, report on failures, and find test suite problems.

[berlin-with0ut-return]

there's some stylistic fixes that'll be needed to upstream this but overall the logic looks good

[os-d]

Between @berlin-with0ut-return 's changes here and this, I assume we will upstream the changes?

[eeshanl]

Between @berlin-with0ut-return 's changes here and this, I assume we will upstream the changes?

@berlin-with0ut-return's changes have already been upstreamed. However, this PR will also need to be upstreamed, yes.