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This project utilizes a Verilog Register Transfer Level hardware implementation to convert compressed bitstream data to its original uncompressed 320x240 pixel image. This project involves interfacing with various controllers (eg. VGA, UART), developing a state table to establish Finite State Machines to load data, perform matrix multiplication,…

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Clock_100_PLL.v
Clock_100_PLL.v
 
 
PB_Controller.v
PB_Controller.v
 
 
README.md
README.md
 
 
SRAM_Controller.v
SRAM_Controller.v
 
 
UART_Receive_Controller.v
UART_Receive_Controller.v
 
 
UART_SRAM_interface.v
UART_SRAM_interface.v
 
 
VGA_Controller.v
VGA_Controller.v
 
 
VGA_Param.h
VGA_Param.h
 
 
VGA_SRAM_interface.v
VGA_SRAM_interface.v
 
 
add_my_waveforms.do
add_my_waveforms.do
 
 
convert_hex_to_seven_segment.v
convert_hex_to_seven_segment.v
 
 
define_state.h
define_state.h
 
 
dual_port_RAM0.hex
dual_port_RAM0.hex
 
 
dual_port_RAM0.mif
dual_port_RAM0.mif
 
 
dual_port_RAM0.v
dual_port_RAM0.v
 
 
dual_port_RAM1.hex
dual_port_RAM1.hex
 
 
dual_port_RAM1.mif
dual_port_RAM1.mif
 
 
dual_port_RAM1.v
dual_port_RAM1.v
 
 
fundamental_milestone.v
fundamental_milestone.v
 
 
project.do
project.do
 
 
project.qsf
project.qsf
 
 
project.v
project.v
 
 
tb_SRAM_Emulator.v
tb_SRAM_Emulator.v
 
 
tb_project.v
tb_project.v
 
 
tb_project_v2.v
tb_project_v2.v
 
 
the_cosine_milestone.v
the_cosine_milestone.v
 
 
the_maariz_milestone.v
the_maariz_milestone.v
 
 

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Hardware Image Decompression Algorithm

Introduction

This project utilizes a Verilog Register Transfer Level hardware implementation to convert compressed bitstream data to its original uncompressed 320x240 pixel image. This project involves interfacing with various controllers (eg. VGA, UART), developing a state table to establish Finite State Machines to load data, perform matrix multiplication, and reading/writing data back to RAM given finite resources (RAM, Multiplication units).

About

This project utilizes a Verilog Register Transfer Level hardware implementation to convert compressed bitstream data to its original uncompressed 320x240 pixel image. This project involves interfacing with various controllers (eg. VGA, UART), developing a state table to establish Finite State Machines to load data, perform matrix multiplication,…

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algorithm fpga image-processing fourier-transform verilog-project bitstreams

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