A shared repository between Software, Embedded and FPGA teams to handle sending and receiving ultrasonic waves from the appropriate transducers. The project is based on Xilinix Zynq7000 board.
The FPGA block in this system is reponsible for bridging the gap between the PS and the transducer. It aims to transfer the order coming from the PS which comes firstly from the GUI to the transducer. The Block is also responsible for getting rid of the spikes in the received data and setting tags for each received sample along with sending it back to the PS.
- Verification Plan
- Coverage Report
- Top module File
- Top module Interface File
- UVM Top module File
- Golden Model File
- Golden Model Interface
- UVM Test package
- UVM Environment package
- UVM Agent package
- UVM Driver package
- UVM Monitor package
- UVM Sequencer package
- UVM Sequence package
- UVM Sequence Item package
- UVM Scoreboard package
- UVM Coverage Collector package
The control unit is responsible for receiving the control word from the decoder and performing based on it whether to activate the sending unit or the receiving unit or even the both units. The sending unit is responsible for adjusting the DAC with the desired power value and checking the validity of the control word. The receiving unit is reponsible for getting data from the buffer unit and transferring it through the AXI port to the PS unit. Moreover, the whole unit is responsible for checking that the whole system haven't reached the maximum number of transferring orders yet.
- Receiving Unit Design File
- Sending Unit Design File
- The RAM connected to the CU output
- Top Module
- Receive-block Control Unit Testbench
- Control Unit Testbench
- CU Testbench package
The decoder's role is to receive the control word from the PS and decoding it to the control unit.
The buffer is responsible for processing the data coming from the FIFO through getting rid of spikes through averaging and adding tags to each received sample.