Skip to content

[rom_ctrl,rtl] Add a flop between rom_ctrl and kmac #27658

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 3 commits into
base: master
Choose a base branch
from
Open
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
12 changes: 12 additions & 0 deletions hw/ip/rom_ctrl/data/rom_ctrl.hjson
Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,18 @@
expose: "true"
}

{ name: "FlopToKmac",
type: "bit",
desc: '''
Add a flop stage between the output of the ROM and the data that gets
sent to KMAC. This may break long paths in a target chip, at the cost of
adding chip area.
'''
local: "false",
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I think it would be better to make it local: "true" so that it becomes an localparam and the top-level HJSON is the single source of truth.

expose: "true",
default: "1'b0"
}

{ name: "RndCnstScrNonce",
type: "bit [63:0]",
desc: "Fixed nonce used for address / data scrambling"
Expand Down
74 changes: 63 additions & 11 deletions hw/ip/rom_ctrl/rtl/rom_ctrl.sv
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,15 @@ module rom_ctrl
parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
// Number of cycles a differential skew is tolerated on the alert signal
parameter int unsigned AlertSkewCycles = 1,
// If FlopToKmac is true, insert a flop stage between the output of the ROM and the data that gets
// sent to KMAC. This path might be long in a target design and inserting this flop breaks the
// path at the cost of chip area.
//
// Note that this works by adding a FIFO. This would work with just one item in the FIFO, but
// splitting the long path means that the bandwidth halves (because the ready signal from KMAC
// isn't fed through to the ROM). The code below sets Depth=2 to maintain bandwidth, but Depth=1
// would also work, at the cost of halving bandwidth.
parameter bit FlopToKmac = 1'b0,
parameter bit [63:0] RndCnstScrNonce = '0,
parameter bit [127:0] RndCnstScrKey = '0,
// ROM size in bytes
Expand Down Expand Up @@ -78,16 +87,16 @@ module rom_ctrl

logic [RomIndexWidth-1:0] checker_rom_index;
logic checker_rom_req;
logic [DataWidth-1:0] checker_rom_rdata;
logic [DataWidth-1:0] checker_rom_rdata, checker_rom_rdata_outer;

logic internal_alert;

// Pack / unpack kmac connection data ========================================

logic [63:0] kmac_rom_data;
logic kmac_rom_rdy;
logic kmac_rom_vld;
logic kmac_rom_last;
logic kmac_rom_rdy, kmac_rom_rdy_outer;
logic kmac_rom_vld, kmac_rom_vld_outer;
logic kmac_rom_last, kmac_rom_last_outer;
logic kmac_done;
logic [255:0] kmac_digest;
logic kmac_err;
Expand Down Expand Up @@ -118,12 +127,12 @@ module rom_ctrl
localparam int NumBytes = (DataWidth + 7) / 8;

// SEC_CM: MEM.DIGEST
assign kmac_data_o = '{valid: kmac_rom_vld,
assign kmac_data_o = '{valid: kmac_rom_vld_outer,
data: kmac_rom_data,
strb: kmac_pkg::MsgStrbW'({NumBytes{1'b1}}),
last: kmac_rom_last};
last: kmac_rom_last_outer};

assign kmac_rom_rdy = kmac_data_i.ready;
assign kmac_rom_rdy_outer = kmac_data_i.ready;
assign kmac_done = kmac_data_i.done;
assign kmac_digest = kmac_data_i.digest_share0[255:0] ^ kmac_data_i.digest_share1[255:0];
assign kmac_err = kmac_data_i.error;
Expand All @@ -139,7 +148,7 @@ module rom_ctrl
// Scrambling is disabled. Stub out all KMAC connections and waive the ignored signals.

assign kmac_data_o = '0;
assign kmac_rom_rdy = 1'b0;
assign kmac_rom_rdy_outer = 1'b0;
assign kmac_done = 1'b0;
assign kmac_digest = '0;
assign kmac_err = 1'b0;
Expand Down Expand Up @@ -312,7 +321,7 @@ module rom_ctrl
end : gen_rom_scramble_disabled

// Zero expand checker rdata to pass to KMAC
assign kmac_rom_data = {{64-DataWidth{1'b0}}, checker_rom_rdata};
assign kmac_rom_data = {{64-DataWidth{1'b0}}, checker_rom_rdata_outer};

// Register block ============================================================

Expand Down Expand Up @@ -371,6 +380,48 @@ module rom_ctrl
.alert_o (checker_alert)
);

if (FlopToKmac) begin : gen_kmac_flopped_output
// If there is a flop between the ROM and KMAC then we distinguish between the data that is
// connected to the ROM itself and the version that is connected to KMAC. The latter signals
// have an "_outer" suffix.
//
// Note that for data coming out of the block (e.g. kmac_rom_vld), the "_outer" signal is
// later than the undecorated version. For data coming into the block (e.g. kmac_rom_rdy), the
// "_outer" signal is earlier than the undecorated version.

prim_fifo_sync #(
.Width(1 + DataWidth),
.Pass(1'b0),
.Depth(2),
.OutputZeroIfEmpty(1'b0),
.NeverClears(1'b1),
.Secure(0)
) u_kmac_data_flop (
.clk_i,
.rst_ni,
.clr_i (1'b0),
.wvalid_i (kmac_rom_vld),
.wready_o (kmac_rom_rdy),
.wdata_i ({kmac_rom_last, checker_rom_rdata}),
.rvalid_o (kmac_rom_vld_outer),
.rready_i (kmac_rom_rdy_outer),
.rdata_o ({kmac_rom_last_outer, checker_rom_rdata_outer}),
.full_o (),
.depth_o (),
.err_o ()
);
end else begin : gen_kmac_direct_output
// If there is not a flop on the output, the "_outer" version of a signal is exactly the same
// as the underlying signal.

assign kmac_rom_vld_outer = kmac_rom_vld;
assign kmac_rom_last_outer = kmac_rom_last;
assign checker_rom_rdata_outer = checker_rom_rdata;

assign kmac_rom_rdy = kmac_rom_rdy_outer;
end


end : gen_fsm_scramble_enabled
else begin : gen_fsm_scramble_disabled

Expand All @@ -387,8 +438,9 @@ module rom_ctrl
// zeros" check.
assign keymgr_data_o = '{data: {128{2'b10}}, valid: 1'b1};

assign kmac_rom_vld = 1'b0;
assign kmac_rom_last = 1'b0;
assign kmac_rom_vld = 1'b0;
assign kmac_rom_vld_outer = 1'b0;
assign kmac_rom_last = 1'b0;

// Always grant access to the bus. Setting this to a constant should mean the mux gets
// synthesized away completely.
Expand Down
30 changes: 30 additions & 0 deletions hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson
Original file line number Diff line number Diff line change
Expand Up @@ -7769,6 +7769,7 @@
param_decl:
{
SecDisableScrambling: 1'b0
FlopToKmac: 1'b1
}
clock_connections:
{
Expand All @@ -7785,6 +7786,20 @@
expose: "true"
name_top: RomCtrl0BootRomInitFile
}
{
name: FlopToKmac
desc:
'''
Add a flop stage between the output of the ROM and the data that gets
sent to KMAC. This may break long paths in a target chip, at the cost of
adding chip area.
'''
type: bit
default: 1'b1
local: "false"
expose: "true"
name_top: RomCtrl0FlopToKmac
}
{
name: RndCnstScrNonce
desc: Fixed nonce used for address / data scrambling
Expand Down Expand Up @@ -7955,6 +7970,7 @@
param_decl:
{
SecDisableScrambling: 1'b0
FlopToKmac: 1'b1
}
clock_connections:
{
Expand All @@ -7971,6 +7987,20 @@
expose: "true"
name_top: RomCtrl1BootRomInitFile
}
{
name: FlopToKmac
desc:
'''
Add a flop stage between the output of the ROM and the data that gets
sent to KMAC. This may break long paths in a target chip, at the cost of
adding chip area.
'''
type: bit
default: 1'b1
local: "false"
expose: "true"
name_top: RomCtrl1FlopToKmac
}
{
name: RndCnstScrNonce
desc: Fixed nonce used for address / data scrambling
Expand Down
6 changes: 4 additions & 2 deletions hw/top_darjeeling/data/top_darjeeling.hjson
Original file line number Diff line number Diff line change
Expand Up @@ -887,7 +887,8 @@
}
},
param_decl: {
SecDisableScrambling: "1'b0"
SecDisableScrambling: "1'b0",
FlopToKmac: "1'b1"
}
},
{ name: "rom_ctrl1",
Expand All @@ -913,7 +914,8 @@
}
},
param_decl: {
SecDisableScrambling: "1'b0"
SecDisableScrambling: "1'b0",
FlopToKmac: "1'b1"
}
},
{ name: "dma",
Expand Down
4 changes: 4 additions & 0 deletions hw/top_darjeeling/rtl/autogen/top_darjeeling.sv
Original file line number Diff line number Diff line change
Expand Up @@ -108,9 +108,11 @@ module top_darjeeling #(
parameter bit SramCtrlMboxEccCorrection = 0,
// parameters for rom_ctrl0
parameter RomCtrl0BootRomInitFile = "",
parameter bit RomCtrl0FlopToKmac = 1'b1,
parameter bit SecRomCtrl0DisableScrambling = 1'b0,
// parameters for rom_ctrl1
parameter RomCtrl1BootRomInitFile = "",
parameter bit RomCtrl1FlopToKmac = 1'b1,
parameter bit SecRomCtrl1DisableScrambling = 1'b0,
// parameters for dma
parameter bit DmaEnableDataIntgGen = 1'b1,
Expand Down Expand Up @@ -2255,6 +2257,7 @@ module top_darjeeling #(
.AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[72:72]),
.AlertSkewCycles(top_pkg::AlertSkewCycles),
.BootRomInitFile(RomCtrl0BootRomInitFile),
.FlopToKmac(RomCtrl0FlopToKmac),
.RndCnstScrNonce(RndCnstRomCtrl0ScrNonce),
.RndCnstScrKey(RndCnstRomCtrl0ScrKey),
.SecDisableScrambling(SecRomCtrl0DisableScrambling),
Expand Down Expand Up @@ -2283,6 +2286,7 @@ module top_darjeeling #(
.AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[73:73]),
.AlertSkewCycles(top_pkg::AlertSkewCycles),
.BootRomInitFile(RomCtrl1BootRomInitFile),
.FlopToKmac(RomCtrl1FlopToKmac),
.RndCnstScrNonce(RndCnstRomCtrl1ScrNonce),
.RndCnstScrKey(RndCnstRomCtrl1ScrKey),
.SecDisableScrambling(SecRomCtrl1DisableScrambling),
Expand Down
14 changes: 14 additions & 0 deletions hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
Original file line number Diff line number Diff line change
Expand Up @@ -9413,6 +9413,20 @@
expose: "true"
name_top: RomCtrlBootRomInitFile
}
{
name: FlopToKmac
desc:
'''
Add a flop stage between the output of the ROM and the data that gets
sent to KMAC. This may break long paths in a target chip, at the cost of
adding chip area.
'''
type: bit
default: 1'b0
local: "false"
expose: "true"
name_top: RomCtrlFlopToKmac
}
{
name: RndCnstScrNonce
desc: Fixed nonce used for address / data scrambling
Expand Down
2 changes: 2 additions & 0 deletions hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
Original file line number Diff line number Diff line change
Expand Up @@ -118,6 +118,7 @@ module top_earlgrey #(
parameter bit SramCtrlMainEccCorrection = 0,
// parameters for rom_ctrl
parameter RomCtrlBootRomInitFile = "",
parameter bit RomCtrlFlopToKmac = 1'b0,
parameter bit SecRomCtrlDisableScrambling = 1'b0,
// parameters for rv_core_ibex
parameter bit RvCoreIbexPMPEnable = 1,
Expand Down Expand Up @@ -2783,6 +2784,7 @@ module top_earlgrey #(
.AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[60:60]),
.AlertSkewCycles(top_pkg::AlertSkewCycles),
.BootRomInitFile(RomCtrlBootRomInitFile),
.FlopToKmac(RomCtrlFlopToKmac),
.RndCnstScrNonce(RndCnstRomCtrlScrNonce),
.RndCnstScrKey(RndCnstRomCtrlScrKey),
.SecDisableScrambling(SecRomCtrlDisableScrambling),
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -4122,6 +4122,20 @@
expose: "true"
name_top: RomCtrlBootRomInitFile
}
{
name: FlopToKmac
desc:
'''
Add a flop stage between the output of the ROM and the data that gets
sent to KMAC. This may break long paths in a target chip, at the cost of
adding chip area.
'''
type: bit
default: 1'b0
local: "false"
expose: "true"
name_top: RomCtrlFlopToKmac
}
{
name: RndCnstScrNonce
desc: Fixed nonce used for address / data scrambling
Expand Down
2 changes: 2 additions & 0 deletions hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast.sv
Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,7 @@ module top_englishbreakfast #(
parameter bit SramCtrlMainEccCorrection = 0,
// parameters for rom_ctrl
parameter RomCtrlBootRomInitFile = "",
parameter bit RomCtrlFlopToKmac = 1'b0,
parameter bit SecRomCtrlDisableScrambling = 1'b1,
// parameters for rv_core_ibex
parameter bit RvCoreIbexPMPEnable = 0,
Expand Down Expand Up @@ -1244,6 +1245,7 @@ module top_englishbreakfast #(
.AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[23:23]),
.AlertSkewCycles(top_pkg::AlertSkewCycles),
.BootRomInitFile(RomCtrlBootRomInitFile),
.FlopToKmac(RomCtrlFlopToKmac),
.RndCnstScrNonce(RndCnstRomCtrlScrNonce),
.RndCnstScrKey(RndCnstRomCtrlScrKey),
.SecDisableScrambling(SecRomCtrlDisableScrambling),
Expand Down
Loading