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lines changed Original file line number Diff line number Diff line change @@ -787,7 +787,7 @@ class cip_base_vseq #(
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// accesses can also be set by derived classes for special cases. If the wait doesn't clear
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// something is probably wrong: perhaps some loop sending CSR transactions is missing a
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// break if stop_transaction_generators() is set.
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- virtual task wait_to_issue_reset (uint reset_delay_bound = 10_000_000 );
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+ virtual task wait_to_issue_reset (uint reset_delay_bound);
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int cycles_with_no_accesses = 0 ;
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int cycles_waited;
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Original file line number Diff line number Diff line change @@ -28,7 +28,7 @@ class hmac_common_vseq extends hmac_base_vseq;
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run_common_vseq_wrapper (num_trans);
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endtask : body
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- virtual task wait_to_issue_reset (uint reset_delay_bound = 10_000_000 );
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+ virtual task wait_to_issue_reset (uint reset_delay_bound);
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`DV_CHECK_MEMBER_RANDOMIZE_FATAL (trig_rst_during_hash)
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if (trig_rst_during_hash) begin
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