[top_earlgrey/rtl] Connect IOB mux from AST to padring

Together with the previous commit, this resolves #23280.

Signed-off-by: Andreas Kurth <adk@lowrisc.org>

Author: andreaskurth

hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv

@@ -196,6 +196,8 @@ module chip_earlgrey_asic #(
   ////////////////////////
 
 
+  logic [3:0] mux_iob_sel;
+
   pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr;
   pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr;
   logic [pinmux_reg_pkg::NMioPads-1:0] mio_out;
@@ -477,7 +479,7 @@ module chip_earlgrey_asic #(
   // This is only used for scan and DFT purposes
     .clk_scan_i   ( ast_base_clks.clk_sys ),
     .scanmode_i   ( scanmode              ),
-    .mux_iob_sel_i ('0), // TODO(#23280)
+    .mux_iob_sel_i ( mux_iob_sel ),
     .dio_in_raw_o ( dio_in_raw ),
     // Chip IOs
     .dio_pad_io ({
@@ -968,6 +970,7 @@ module chip_earlgrey_asic #(
     // pinmux related
     .padmux2ast_i          ( pad2ast    ),
     .ast2padmux_o          ( ast2pinmux ),
+    .mux_iob_sel_o         ( mux_iob_sel ),
     .ext_freq_is_96m_i     ( hi_speed_sel ),
     .all_clk_byp_req_i     ( all_clk_byp_req  ),
     .all_clk_byp_ack_o     ( all_clk_byp_ack  ),

hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv

@@ -206,6 +206,8 @@ module chip_earlgrey_cw310 #(
   ////////////////////////
 
 
+  logic [3:0] mux_iob_sel;
+
   pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr;
   pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr;
   logic [pinmux_reg_pkg::NMioPads-1:0] mio_out;
@@ -355,7 +357,7 @@ module chip_earlgrey_cw310 #(
   // This is only used for scan and DFT purposes
     .clk_scan_i   ( 1'b0                  ),
     .scanmode_i   ( prim_mubi_pkg::MuBi4False ),
-    .mux_iob_sel_i ('0), // TODO(#23280)
+    .mux_iob_sel_i ( mux_iob_sel ),
     .dio_in_raw_o ( dio_in_raw ),
     // Chip IOs
     .dio_pad_io ({
@@ -940,6 +942,7 @@ module chip_earlgrey_cw310 #(
     // pinmux related
     .padmux2ast_i          ( pad2ast    ),
     .ast2padmux_o          ( ast2pinmux ),
+    .mux_iob_sel_o         ( mux_iob_sel ),
     .ext_freq_is_96m_i     ( hi_speed_sel ),
     .all_clk_byp_req_i     ( all_clk_byp_req  ),
     .all_clk_byp_ack_o     ( all_clk_byp_ack  ),

hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw340.sv

@@ -205,6 +205,8 @@ module chip_earlgrey_cw340 #(
   ////////////////////////
 
 
+  logic [3:0] mux_iob_sel;
+
   pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr;
   pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr;
   logic [pinmux_reg_pkg::NMioPads-1:0] mio_out;
@@ -351,7 +353,7 @@ module chip_earlgrey_cw340 #(
   // This is only used for scan and DFT purposes
     .clk_scan_i   ( 1'b0                  ),
     .scanmode_i   ( prim_mubi_pkg::MuBi4False ),
-    .mux_iob_sel_i ('0), // TODO(#23280)
+    .mux_iob_sel_i ( mux_iob_sel ),
     .dio_in_raw_o ( dio_in_raw ),
     // Chip IOs
     .dio_pad_io ({
@@ -931,6 +933,7 @@ module chip_earlgrey_cw340 #(
     // pinmux related
     .padmux2ast_i          ( pad2ast    ),
     .ast2padmux_o          ( ast2pinmux ),
+    .mux_iob_sel_o         ( mux_iob_sel ),
     .ext_freq_is_96m_i     ( hi_speed_sel ),
     .all_clk_byp_req_i     ( all_clk_byp_req  ),
     .all_clk_byp_ack_o     ( all_clk_byp_ack  ),

util/topgen/templates/chiplevel.sv.tpl

@@ -182,6 +182,8 @@ module chip_${top["name"]}_${target["name"]} #(
   wire ${port};
   % endfor
 
+  logic [3:0] mux_iob_sel;
+
   pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr;
   pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr;
   logic [pinmux_reg_pkg::NMioPads-1:0] mio_out;
@@ -310,7 +312,7 @@ module chip_${top["name"]}_${target["name"]} #(
     .clk_scan_i   ( 1'b0                  ),
     .scanmode_i   ( prim_mubi_pkg::MuBi4False ),
   % endif
-    .mux_iob_sel_i ('0), // TODO(#23280)
+    .mux_iob_sel_i ( mux_iob_sel ),
     .dio_in_raw_o ( dio_in_raw ),
     // Chip IOs
     .dio_pad_io ({
@@ -842,6 +844,7 @@ module chip_${top["name"]}_${target["name"]} #(
     // pinmux related
     .padmux2ast_i          ( pad2ast    ),
     .ast2padmux_o          ( ast2pinmux ),
+    .mux_iob_sel_o         ( mux_iob_sel ),
     .ext_freq_is_96m_i     ( hi_speed_sel ),
     .all_clk_byp_req_i     ( all_clk_byp_req  ),
     .all_clk_byp_ack_o     ( all_clk_byp_ack  ),