Is it possible to get 1 unique tile?

[mustafaarslan0]

I want to know is it possible to get 1 unique tile with OpenFPGA. All switch boxes and connection boxes will be same. Corner and perimeter blocks can increase area (with unused connections) but it will provide much simpler physical design. @tangxifan

[tangxifan]

@mustafaarslan0 In the core fabric, I believe it is doable. You may have to craft your routing resource graph. We have something experimental like VIB in VPR now. It will give you full freedom on routing architecture. If you are interested, we can collaborate.