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[msan] Check mask and rounding mode in handleAVX512VectorConvertFPToInt #147782

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Merged
merged 2 commits into from
Jul 9, 2025
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[msan] Check mask and rounding mode in handleAVX512VectorConvertFPToInt #147782

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[msan] Check mask and rounding mode in handleAVX512VectorConvertFPToInt
thurstond Jul 9, 2025
b4b203b
Add comment about rounding mode
thurstond Jul 9, 2025
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7 changes: 6 additions & 1 deletion llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4391,7 +4391,7 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
Value *A = I.getOperand(0);
Value *WriteThrough = I.getOperand(1);
Value *Mask = I.getOperand(2);
[[maybe_unused]] Value *RoundingMode = I.getOperand(3);
Value *RoundingMode = I.getOperand(3);

assert(isa<FixedVectorType>(A->getType()));
assert(A->getType()->isFPOrFPVectorTy());
Expand All @@ -4406,8 +4406,13 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {

assert(Mask->getType()->isIntegerTy());
assert(Mask->getType()->getScalarSizeInBits() == ANumElements);
insertCheckShadowOf(Mask, &I);

assert(RoundingMode->getType()->isIntegerTy());
// Only four bits of the rounding mode are used, though it's very
// unusual to have uninitialized bits there (more commonly, it's a
// constant).
insertCheckShadowOf(RoundingMode, &I);
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Just confirming that the implementation doesn't just look at a few bits of this?

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I think technically only 4 out of the 16 bits are used, though I would think mistakes were made if someone was intentionally only initializing the necessary bits. (I expect the rounding mode is more commonly a constant e.g., as seen in avx512-intrinsics.ll. In that case, the shadow check is actually elided.)

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Please leave a comment to that effect. So we remember in case your expectation turns out to be wrong.

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Done


assert(I.getType() == WriteThrough->getType());

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7 changes: 7 additions & 0 deletions llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics.ll
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Expand Up @@ -7941,13 +7941,20 @@ declare <16 x i32> @llvm.x86.avx512.mask.cvtps2dq.512(<16 x float>, <16 x i32>,

define <16 x i32>@test_int_x86_avx512_mask_cvt_ps2dq_512(<16 x float> %x0, <16 x i32> %x1, i16 %x2) #0 {
; CHECK-LABEL: @test_int_x86_avx512_mask_cvt_ps2dq_512(
; CHECK-NEXT: [[TMP10:%.*]] = load i16, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 128) to ptr), align 8
; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8
; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP3:%.*]] = bitcast i16 [[X2:%.*]] to <16 x i1>
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <16 x i32> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = sext <16 x i1> [[TMP4]] to <16 x i32>
; CHECK-NEXT: [[TMP6:%.*]] = select <16 x i1> [[TMP3]], <16 x i32> [[TMP5]], <16 x i32> [[TMP2]]
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i16 [[TMP10]], 0
; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP11:%.*]], label [[TMP12:%.*]], !prof [[PROF1]]
; CHECK: 8:
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]
; CHECK-NEXT: unreachable
; CHECK: 9:
; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.mask.cvtps2dq.512(<16 x float> [[X0:%.*]], <16 x i32> [[X1:%.*]], i16 [[X2]], i32 10)
; CHECK-NEXT: [[TMP7:%.*]] = icmp ne <16 x i32> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = sext <16 x i1> [[TMP7]] to <16 x i32>
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