Skip to content

[RISCV] Add scheduling info for XSfvqmaccdod/qoq and XSfvfwmaccqqq instructions #147626

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Jul 9, 2025
Merged

[RISCV] Add scheduling info for XSfvqmaccdod/qoq and XSfvfwmaccqqq instructions #147626

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
16ee057
[RISCV] Add scheduling info for XSfvqmaccdod/qoq and XSfvfwmaccqqq in…
mshockwave Jul 9, 2025
a93615f
Merge remote-tracking branch 'origin/main' into patch/rvv/xsfvqmacc-s…
mshockwave Jul 9, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
23 changes: 21 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -167,10 +167,25 @@ multiclass CustomSiFiveVCIX<string suffix, VCIXType type,
InTyRs1, 1>;
}

// For XSfvqmaccdod/qoq and XSfvfwmaccqqq
class SiFiveVMACCScheds<string name> {
defvar n = !tolower(name);
defvar prefix = !if(!ne(!find(n, "fw"), -1), "FW", "Q");
defvar suffix = !if(!ne(!find(n, "2x8x2"), -1), "DOD",
!if(!eq(prefix, "Q"), "QOQ", "QQQ"));

string read = "ReadSF_V" # prefix # "MACC_" # suffix;
string write = "WriteSF_V" # prefix # "MACC_" # suffix;
}

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
class CustomSiFiveVMACC<bits<6> funct6, RISCVVFormat opv, string opcodestr>
: RVInstVCCustom2<funct6{5-2}, opv.Value, (outs VR:$rd), (ins VR:$rs1, VR:$rs2),
opcodestr, "$rd, $rs1, $rs2"> {
opcodestr, "$rd, $rs1, $rs2">,
SchedTernaryMC<SiFiveVMACCScheds<NAME>.write,
SiFiveVMACCScheds<NAME>.read,
SiFiveVMACCScheds<NAME>.read,
SiFiveVMACCScheds<NAME>.read> {
let vm = 1;
let funct6_lo2 = funct6{1-0};
}
Expand Down Expand Up @@ -374,9 +389,13 @@ multiclass VPseudoVC_XVW<LMULInfo m, DAGOperand RS1Class,
}

multiclass VPseudoSiFiveVMACC<string mx, VReg vd_type, VReg vs2_type> {
defvar SchedWriteName = SiFiveVMACCScheds<NAME>.write;
defvar SchedReadName = SiFiveVMACCScheds<NAME>.read;
def "Pseudo" # NAME # "_" # mx
: VPseudoTernaryNoMaskWithPolicy<vd_type, V_M1.vrclass, vs2_type,
"@earlyclobber $rd">;
"@earlyclobber $rd">,
SchedTernary<SchedWriteName, SchedReadName, SchedReadName,
SchedReadName, mx>;
}

multiclass VPseudoSiFiveVQMACCDOD {
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSchedAndes45.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -332,6 +332,9 @@ defm : UnsupportedSchedSFB;
defm : UnsupportedSchedV;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedXSfvfnrclipxfqf;
defm : UnsupportedSchedXSfvfwmaccqqq;
defm : UnsupportedSchedXSfvqmaccdod;
defm : UnsupportedSchedXSfvqmaccqoq;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -499,4 +499,7 @@ defm : UnsupportedSchedZvk;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedXSfvfnrclipxfqf;
defm : UnsupportedSchedXSfvfwmaccqqq;
defm : UnsupportedSchedXSfvqmaccdod;
defm : UnsupportedSchedXSfvqmaccqoq;
}
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -275,5 +275,8 @@ defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedXSfvfnrclipxfqf;
defm : UnsupportedSchedXSfvfwmaccqqq;
defm : UnsupportedSchedXSfvqmaccdod;
defm : UnsupportedSchedXSfvqmaccqoq;
defm : UnsupportedSchedZvk;
}
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSchedRocket.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -264,5 +264,8 @@ defm : UnsupportedSchedZfhmin;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedXSfvfnrclipxfqf;
defm : UnsupportedSchedXSfvfwmaccqqq;
defm : UnsupportedSchedXSfvqmaccdod;
defm : UnsupportedSchedXSfvqmaccqoq;
defm : UnsupportedSchedZvk;
}
35 changes: 35 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1072,6 +1072,36 @@ multiclass SiFive7WriteResBase<int VLEN,
defm : LMULWriteResMX<"WriteSF_VFNRClipV", [VCQ, VA1], mx,
IsWorstCase=!eq(mx, "M2")>;
}

// XSfvqmaccdod
foreach mx = ["M1", "M2", "M4", "M8"] in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
let Latency = 8,
AcquireAtCycles = [0, 1],
ReleaseAtCycles = [1, !add(1, Cycles)] in
defm : LMULWriteResMX<"WriteSF_VQMACC_DOD", [VCQ, VA1], mx,
IsWorstCase=!eq(mx, "M8")>;
}

// XSfvqmaccqoq
foreach mx = ["MF2", "M1", "M2", "M4"] in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
let Latency = 8,
AcquireAtCycles = [0, 1],
ReleaseAtCycles = [1, !add(1, Cycles)] in
defm : LMULWriteResMX<"WriteSF_VQMACC_QOQ", [VCQ, VA1], mx,
IsWorstCase=!eq(mx, "M4")>;
}

// XSfvfwmaccqqq
foreach mx = SchedMxListFW in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListFW>.c;
let Latency = 8,
AcquireAtCycles = [0, 1],
ReleaseAtCycles = [1, !add(1, Cycles)] in
defm : LMULWriteResMX<"WriteSF_VFWMACC_QQQ", [VCQ, VA1], mx, IsWorstCase>;
}
}

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -1353,6 +1383,11 @@ multiclass SiFive7ReadAdvance {
defm : LMULReadAdvance<"ReadSF_VFNRClipV", 0>;
defm : LMULReadAdvance<"ReadSF_VFNRClipF", 0>;

// SiFive VMACC
defm : LMULReadAdvance<"ReadSF_VQMACC_DOD", 0>;
defm : LMULReadAdvance<"ReadSF_VQMACC_QOQ", 0>;
defm : LMULReadAdvance<"ReadSF_VFWMACC_QQQ", 0>;

// Others
def : ReadAdvance<ReadVMask, 0>;
def : ReadAdvance<ReadVPassthru_WorstCase, 0>;
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1240,4 +1240,7 @@ defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedXSfvfnrclipxfqf;
defm : UnsupportedSchedXSfvfwmaccqqq;
defm : UnsupportedSchedXSfvqmaccdod;
defm : UnsupportedSchedXSfvqmaccqoq;
}
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -360,4 +360,7 @@ defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZvk;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedXSfvfnrclipxfqf;
defm : UnsupportedSchedXSfvfwmaccqqq;
defm : UnsupportedSchedXSfvqmaccdod;
defm : UnsupportedSchedXSfvqmaccqoq;
}
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1496,4 +1496,7 @@ defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedXSfvfnrclipxfqf;
defm : UnsupportedSchedXSfvfwmaccqqq;
defm : UnsupportedSchedXSfvqmaccdod;
defm : UnsupportedSchedXSfvqmaccqoq;
}
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1185,4 +1185,7 @@ defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZfaWithQ;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedXSfvfnrclipxfqf;
defm : UnsupportedSchedXSfvfwmaccqqq;
defm : UnsupportedSchedXSfvqmaccdod;
defm : UnsupportedSchedXSfvqmaccqoq;
}
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -347,6 +347,9 @@ defm : UnsupportedSchedQ;
defm : UnsupportedSchedV;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedXSfvfnrclipxfqf;
defm : UnsupportedSchedXSfvfwmaccqqq;
defm : UnsupportedSchedXSfvqmaccdod;
defm : UnsupportedSchedXSfvqmaccqoq;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -118,5 +118,8 @@ defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedXSfvfnrclipxfqf;
defm : UnsupportedSchedXSfvfwmaccqqq;
defm : UnsupportedSchedXSfvqmaccdod;
defm : UnsupportedSchedXSfvqmaccqoq;
defm : UnsupportedSchedZvk;
}
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -184,6 +184,9 @@ multiclass SCR_Unsupported :
UnsupportedSchedV,
UnsupportedSchedXsfvcp,
UnsupportedSchedXSfvfnrclipxfqf,
UnsupportedSchedXSfvfwmaccqqq,
UnsupportedSchedXSfvqmaccdod,
UnsupportedSchedXSfvqmaccqoq,
UnsupportedSchedZabha,
UnsupportedSchedZba,
UnsupportedSchedZbb,
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -246,6 +246,9 @@ multiclass SCR7_Unsupported {
defm : UnsupportedSchedV;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedXSfvfnrclipxfqf;
defm : UnsupportedSchedXSfvfwmaccqqq;
defm : UnsupportedSchedXSfvqmaccdod;
defm : UnsupportedSchedXSfvqmaccqoq;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZfhmin;
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -322,6 +322,9 @@ defm : UnsupportedSchedQ;
defm : UnsupportedSchedV;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedXSfvfnrclipxfqf;
defm : UnsupportedSchedXSfvfwmaccqqq;
defm : UnsupportedSchedXSfvqmaccdod;
defm : UnsupportedSchedXSfvqmaccqoq;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedZbc;
defm : UnsupportedSchedZbkb;
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -314,5 +314,8 @@ defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedXSfvfnrclipxfqf;
defm : UnsupportedSchedXSfvfwmaccqqq;
defm : UnsupportedSchedXSfvqmaccdod;
defm : UnsupportedSchedXSfvqmaccqoq;
defm : UnsupportedSchedZvk;
}
30 changes: 30 additions & 0 deletions llvm/lib/Target/RISCV/RISCVScheduleXSf.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -69,3 +69,33 @@ defm : LMULReadAdvance<"ReadSF_VFNRClipV", 0>;
defm : LMULReadAdvance<"ReadSF_VFNRClipF", 0>;
} // Unsupported = true
}

defm "" : LMULSchedWritesImpl<"WriteSF_VQMACC_DOD", ["M1", "M2", "M4", "M8"]>;
defm "" : LMULSchedReadsImpl<"ReadSF_VQMACC_DOD", ["M1", "M2", "M4", "M8"]>;

multiclass UnsupportedSchedXSfvqmaccdod {
let Unsupported = true in {
defm : LMULWriteRes<"WriteSF_VQMACC_DOD", []>;
defm : LMULReadAdvance<"ReadSF_VQMACC_DOD", 0>;
} // Unsupported = true
}

defm "" : LMULSchedWritesImpl<"WriteSF_VQMACC_QOQ", ["MF2", "M1", "M2", "M4"]>;
defm "" : LMULSchedReadsImpl<"ReadSF_VQMACC_QOQ", ["MF2", "M1", "M2", "M4"]>;

multiclass UnsupportedSchedXSfvqmaccqoq {
let Unsupported = true in {
defm : LMULWriteRes<"WriteSF_VQMACC_QOQ", []>;
defm : LMULReadAdvance<"ReadSF_VQMACC_QOQ", 0>;
} // Unsupported = true
}

defm "" : LMULSchedWritesImpl<"WriteSF_VFWMACC_QQQ", SchedMxListFW>;
defm "" : LMULSchedReadsImpl<"ReadSF_VFWMACC_QQQ", SchedMxListFW>;

multiclass UnsupportedSchedXSfvfwmaccqqq {
let Unsupported = true in {
defm : LMULWriteRes<"WriteSF_VFWMACC_QQQ", []>;
defm : LMULReadAdvance<"ReadSF_VFWMACC_QQQ", 0>;
} // Unsupported = true
}
75 changes: 75 additions & 0 deletions llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvfwmacc.s
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,75 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -mattr='+xsfvfwmaccqqq' -instruction-tables=full -iterations=1 %s | \
# RUN: FileCheck %s

vsetvli zero, zero, e16, mf4, ta, ma
sf.vfwmacc.4x4x4 v16, v0, v8
vsetvli zero, zero, e16, mf2, ta, ma
sf.vfwmacc.4x4x4 v16, v0, v8
vsetvli zero, zero, e16, m1, ta, ma
sf.vfwmacc.4x4x4 v16, v0, v8
vsetvli zero, zero, e16, m2, ta, ma
sf.vfwmacc.4x4x4 v16, v0, v8
vsetvli zero, zero, e16, m4, ta, ma
sf.vfwmacc.4x4x4 v16, v0, v8

# CHECK: Resources:
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv:1
# CHECK-NEXT: [1] - VLEN512SiFive7IDiv:1
# CHECK-NEXT: [2] - VLEN512SiFive7PipeA:1
# CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
# CHECK-NEXT: [4] - VLEN512SiFive7PipeB:1
# CHECK-NEXT: [5] - VLEN512SiFive7VA:1
# CHECK-NEXT: [6] - VLEN512SiFive7VCQ:1
# CHECK-NEXT: [7] - VLEN512SiFive7VL:1
# CHECK-NEXT: [8] - VLEN512SiFive7VS:1

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK-NEXT: [7]: Bypass Latency
# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
# CHECK-NEXT: [9]: LLVM Opcode Name

# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4 v16, v0, v8
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4 v16, v0, v8
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, ta, ma
# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4 v16, v0, v8
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m2, ta, ma
# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4 v16, v0, v8
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m4, ta, ma
# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4 v16, v0, v8

# CHECK: Resources:
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
# CHECK-NEXT: [1] - VLEN512SiFive7IDiv
# CHECK-NEXT: [2] - VLEN512SiFive7PipeA
# CHECK-NEXT: [3] - VLEN512SiFive7PipeB
# CHECK-NEXT: [4] - VLEN512SiFive7VA
# CHECK-NEXT: [5] - VLEN512SiFive7VCQ
# CHECK-NEXT: [6] - VLEN512SiFive7VL
# CHECK-NEXT: [7] - VLEN512SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 5.00 - 21.00 5.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, ta, ma
# CHECK-NEXT: - - - - 2.00 1.00 - - sf.vfwmacc.4x4x4 v16, v0, v8
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, ta, ma
# CHECK-NEXT: - - - - 2.00 1.00 - - sf.vfwmacc.4x4x4 v16, v0, v8
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, ta, ma
# CHECK-NEXT: - - - - 3.00 1.00 - - sf.vfwmacc.4x4x4 v16, v0, v8
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, ta, ma
# CHECK-NEXT: - - - - 5.00 1.00 - - sf.vfwmacc.4x4x4 v16, v0, v8
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, ta, ma
# CHECK-NEXT: - - - - 9.00 1.00 - - sf.vfwmacc.4x4x4 v16, v0, v8
Loading
Loading