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[ARM] Port shouldBeAdjustedToZero to ARM #147565

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35 changes: 33 additions & 2 deletions llvm/lib/Target/ARM/ARMISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4839,14 +4839,45 @@ static bool isFloatingPointZero(SDValue Op) {
return false;
}

static bool shouldBeAdjustedToZero(SDValue LHS, APInt C, ISD::CondCode &CC) {
// setlt and setge are changed to MI and PL for zero respectively, so it is
// safe.
if (C.isAllOnes() && (CC == ISD::SETLE || CC == ISD::SETGT)) {
CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
return true;
}

// On ARM, adds and subs set the V flags correctly, which means the optimizer
// can condense to a single adds/subs
switch (LHS.getOpcode()) {
case ISD::ADD:
case ISD::SUB:
break;
default:
return false;
}

if (C.isOne() && (CC == ISD::SETLT || CC == ISD::SETGE)) {
CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
return true;
}

return false;
}

/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
/// the given operands.
SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
SDValue &ARMcc, SelectionDAG &DAG,
const SDLoc &dl) const {
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
unsigned C = RHSC->getZExtValue();
if (!isLegalICmpImmediate((int32_t)C)) {
APInt CInt = RHSC->getAPIntValue();
unsigned C = CInt.getZExtValue();
if (shouldBeAdjustedToZero(LHS, CInt, CC)) {
// Adjust the constant to zero.
// CC has already been adjusted.
RHS = DAG.getConstant(0, dl, MVT::i32);
} else if (!isLegalICmpImmediate((int32_t)C)) {
// Constant does not fit, try adjusting it by one.
switch (CC) {
default: break;
Expand Down
34 changes: 16 additions & 18 deletions llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -19,10 +19,9 @@ define fastcc ptr @wrongUseOfPostDominate(ptr readonly %s, i32 %off, ptr readnon
; ENABLE: @ %bb.0: @ %entry
; ENABLE-NEXT: .save {r11, lr}
; ENABLE-NEXT: push {r11, lr}
; ENABLE-NEXT: cmn r1, #1
; ENABLE-NEXT: ble .LBB0_7
; ENABLE-NEXT: @ %bb.1: @ %while.cond.preheader
; ENABLE-NEXT: cmp r1, #0
; ENABLE-NEXT: bmi .LBB0_7
; ENABLE-NEXT: @ %bb.1: @ %while.cond.preheader
; ENABLE-NEXT: beq .LBB0_6
; ENABLE-NEXT: @ %bb.2: @ %while.cond.preheader
; ENABLE-NEXT: cmp r0, r2
Expand Down Expand Up @@ -66,16 +65,16 @@ define fastcc ptr @wrongUseOfPostDominate(ptr readonly %s, i32 %off, ptr readnon
; ENABLE-NEXT: mov r0, r3
; ENABLE-NEXT: ldrb r12, [r0, #-1]!
; ENABLE-NEXT: sxtb lr, r12
; ENABLE-NEXT: cmn lr, #1
; ENABLE-NEXT: bgt .LBB0_7
; ENABLE-NEXT: cmp lr, #0
; ENABLE-NEXT: bpl .LBB0_7
; ENABLE-NEXT: @ %bb.11: @ %if.then7
; ENABLE-NEXT: @ in Loop: Header=BB0_7 Depth=1
; ENABLE-NEXT: cmp r0, r2
; ENABLE-NEXT: bls .LBB0_7
; ENABLE-NEXT: @ %bb.12: @ %land.rhs14.preheader
; ENABLE-NEXT: @ in Loop: Header=BB0_7 Depth=1
; ENABLE-NEXT: cmn lr, #1
; ENABLE-NEXT: bgt .LBB0_7
; ENABLE-NEXT: cmp lr, #0
; ENABLE-NEXT: bpl .LBB0_7
; ENABLE-NEXT: @ %bb.13: @ %land.rhs14.preheader
; ENABLE-NEXT: @ in Loop: Header=BB0_7 Depth=1
; ENABLE-NEXT: cmp r12, #191
Expand All @@ -93,9 +92,9 @@ define fastcc ptr @wrongUseOfPostDominate(ptr readonly %s, i32 %off, ptr readnon
; ENABLE-NEXT: @ in Loop: Header=BB0_15 Depth=2
; ENABLE-NEXT: mov r3, r0
; ENABLE-NEXT: ldrsb lr, [r3], #-1
; ENABLE-NEXT: cmn lr, #1
; ENABLE-NEXT: cmp lr, #0
; ENABLE-NEXT: uxtb r12, lr
; ENABLE-NEXT: bgt .LBB0_7
; ENABLE-NEXT: bpl .LBB0_7
; ENABLE-NEXT: @ %bb.17: @ %while.body24.land.rhs14_crit_edge
; ENABLE-NEXT: @ in Loop: Header=BB0_15 Depth=2
; ENABLE-NEXT: cmp r12, #192
Expand All @@ -109,10 +108,9 @@ define fastcc ptr @wrongUseOfPostDominate(ptr readonly %s, i32 %off, ptr readnon
; DISABLE: @ %bb.0: @ %entry
; DISABLE-NEXT: .save {r11, lr}
; DISABLE-NEXT: push {r11, lr}
; DISABLE-NEXT: cmn r1, #1
; DISABLE-NEXT: ble .LBB0_7
; DISABLE-NEXT: @ %bb.1: @ %while.cond.preheader
; DISABLE-NEXT: cmp r1, #0
; DISABLE-NEXT: bmi .LBB0_7
; DISABLE-NEXT: @ %bb.1: @ %while.cond.preheader
; DISABLE-NEXT: beq .LBB0_6
; DISABLE-NEXT: @ %bb.2: @ %while.cond.preheader
; DISABLE-NEXT: cmp r0, r2
Expand Down Expand Up @@ -156,16 +154,16 @@ define fastcc ptr @wrongUseOfPostDominate(ptr readonly %s, i32 %off, ptr readnon
; DISABLE-NEXT: mov r0, r3
; DISABLE-NEXT: ldrb r12, [r0, #-1]!
; DISABLE-NEXT: sxtb lr, r12
; DISABLE-NEXT: cmn lr, #1
; DISABLE-NEXT: bgt .LBB0_7
; DISABLE-NEXT: cmp lr, #0
; DISABLE-NEXT: bpl .LBB0_7
; DISABLE-NEXT: @ %bb.11: @ %if.then7
; DISABLE-NEXT: @ in Loop: Header=BB0_7 Depth=1
; DISABLE-NEXT: cmp r0, r2
; DISABLE-NEXT: bls .LBB0_7
; DISABLE-NEXT: @ %bb.12: @ %land.rhs14.preheader
; DISABLE-NEXT: @ in Loop: Header=BB0_7 Depth=1
; DISABLE-NEXT: cmn lr, #1
; DISABLE-NEXT: bgt .LBB0_7
; DISABLE-NEXT: cmp lr, #0
; DISABLE-NEXT: bpl .LBB0_7
; DISABLE-NEXT: @ %bb.13: @ %land.rhs14.preheader
; DISABLE-NEXT: @ in Loop: Header=BB0_7 Depth=1
; DISABLE-NEXT: cmp r12, #191
Expand All @@ -183,9 +181,9 @@ define fastcc ptr @wrongUseOfPostDominate(ptr readonly %s, i32 %off, ptr readnon
; DISABLE-NEXT: @ in Loop: Header=BB0_15 Depth=2
; DISABLE-NEXT: mov r3, r0
; DISABLE-NEXT: ldrsb lr, [r3], #-1
; DISABLE-NEXT: cmn lr, #1
; DISABLE-NEXT: cmp lr, #0
; DISABLE-NEXT: uxtb r12, lr
; DISABLE-NEXT: bgt .LBB0_7
; DISABLE-NEXT: bpl .LBB0_7
; DISABLE-NEXT: @ %bb.17: @ %while.body24.land.rhs14_crit_edge
; DISABLE-NEXT: @ in Loop: Header=BB0_15 Depth=2
; DISABLE-NEXT: cmp r12, #192
Expand Down
144 changes: 72 additions & 72 deletions llvm/test/CodeGen/ARM/consthoist-icmpimm.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -44,19 +44,19 @@ define i32 @icmp64_sge_0(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV7M-NEXT: ldrd r2, r0, [sp]
; CHECKV7M-NEXT: beq .LBB0_2
; CHECKV7M-NEXT: @ %bb.1: @ %then
; CHECKV7M-NEXT: cmp.w r3, #-1
; CHECKV7M-NEXT: cmp r3, #0
; CHECKV7M-NEXT: mov r3, r0
; CHECKV7M-NEXT: it gt
; CHECKV7M-NEXT: movgt r3, r2
; CHECKV7M-NEXT: cmp.w r1, #-1
; CHECKV7M-NEXT: it gt
; CHECKV7M-NEXT: movgt r0, r2
; CHECKV7M-NEXT: it ge
; CHECKV7M-NEXT: movge r3, r2
; CHECKV7M-NEXT: cmp r1, #0
; CHECKV7M-NEXT: it ge
; CHECKV7M-NEXT: movge r0, r2
; CHECKV7M-NEXT: add r0, r3
; CHECKV7M-NEXT: bx lr
; CHECKV7M-NEXT: .LBB0_2: @ %else
; CHECKV7M-NEXT: cmp.w r1, #-1
; CHECKV7M-NEXT: it gt
; CHECKV7M-NEXT: movgt r0, r2
; CHECKV7M-NEXT: cmp r1, #0
; CHECKV7M-NEXT: it ge
; CHECKV7M-NEXT: movge r0, r2
; CHECKV7M-NEXT: bx lr
;
; CHECKV7A-LABEL: icmp64_sge_0:
Expand All @@ -66,19 +66,19 @@ define i32 @icmp64_sge_0(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV7A-NEXT: lsls r2, r2, #31
; CHECKV7A-NEXT: beq .LBB0_2
; CHECKV7A-NEXT: @ %bb.1: @ %then
; CHECKV7A-NEXT: cmp.w r3, #-1
; CHECKV7A-NEXT: cmp r3, #0
; CHECKV7A-NEXT: mov r2, r0
; CHECKV7A-NEXT: it gt
; CHECKV7A-NEXT: movgt r2, r12
; CHECKV7A-NEXT: cmp.w r1, #-1
; CHECKV7A-NEXT: it gt
; CHECKV7A-NEXT: movgt r0, r12
; CHECKV7A-NEXT: it ge
; CHECKV7A-NEXT: movge r2, r12
; CHECKV7A-NEXT: cmp r1, #0
; CHECKV7A-NEXT: it ge
; CHECKV7A-NEXT: movge r0, r12
; CHECKV7A-NEXT: add r0, r2
; CHECKV7A-NEXT: bx lr
; CHECKV7A-NEXT: .LBB0_2: @ %else
; CHECKV7A-NEXT: cmp.w r1, #-1
; CHECKV7A-NEXT: it gt
; CHECKV7A-NEXT: movgt r0, r12
; CHECKV7A-NEXT: cmp r1, #0
; CHECKV7A-NEXT: it ge
; CHECKV7A-NEXT: movge r0, r12
; CHECKV7A-NEXT: bx lr
br i1 %c, label %then, label %else
then:
Expand Down Expand Up @@ -135,19 +135,19 @@ define i32 @icmp64_sgt_m1(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV7M-NEXT: ldrd r2, r0, [sp]
; CHECKV7M-NEXT: beq .LBB1_2
; CHECKV7M-NEXT: @ %bb.1: @ %then
; CHECKV7M-NEXT: cmp.w r3, #-1
; CHECKV7M-NEXT: cmp r3, #0
; CHECKV7M-NEXT: mov r3, r0
; CHECKV7M-NEXT: it gt
; CHECKV7M-NEXT: movgt r3, r2
; CHECKV7M-NEXT: cmp.w r1, #-1
; CHECKV7M-NEXT: it gt
; CHECKV7M-NEXT: movgt r0, r2
; CHECKV7M-NEXT: it ge
; CHECKV7M-NEXT: movge r3, r2
; CHECKV7M-NEXT: cmp r1, #0
; CHECKV7M-NEXT: it ge
; CHECKV7M-NEXT: movge r0, r2
; CHECKV7M-NEXT: add r0, r3
; CHECKV7M-NEXT: bx lr
; CHECKV7M-NEXT: .LBB1_2: @ %else
; CHECKV7M-NEXT: cmp.w r3, #-1
; CHECKV7M-NEXT: it gt
; CHECKV7M-NEXT: movgt r0, r2
; CHECKV7M-NEXT: cmp r3, #0
; CHECKV7M-NEXT: it ge
; CHECKV7M-NEXT: movge r0, r2
; CHECKV7M-NEXT: bx lr
;
; CHECKV7A-LABEL: icmp64_sgt_m1:
Expand All @@ -157,19 +157,19 @@ define i32 @icmp64_sgt_m1(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV7A-NEXT: lsls r2, r2, #31
; CHECKV7A-NEXT: beq .LBB1_2
; CHECKV7A-NEXT: @ %bb.1: @ %then
; CHECKV7A-NEXT: cmp.w r3, #-1
; CHECKV7A-NEXT: cmp r3, #0
; CHECKV7A-NEXT: mov r2, r0
; CHECKV7A-NEXT: it gt
; CHECKV7A-NEXT: movgt r2, r12
; CHECKV7A-NEXT: cmp.w r1, #-1
; CHECKV7A-NEXT: it gt
; CHECKV7A-NEXT: movgt r0, r12
; CHECKV7A-NEXT: it ge
; CHECKV7A-NEXT: movge r2, r12
; CHECKV7A-NEXT: cmp r1, #0
; CHECKV7A-NEXT: it ge
; CHECKV7A-NEXT: movge r0, r12
; CHECKV7A-NEXT: add r0, r2
; CHECKV7A-NEXT: bx lr
; CHECKV7A-NEXT: .LBB1_2: @ %else
; CHECKV7A-NEXT: cmp.w r3, #-1
; CHECKV7A-NEXT: it gt
; CHECKV7A-NEXT: movgt r0, r12
; CHECKV7A-NEXT: cmp r3, #0
; CHECKV7A-NEXT: it ge
; CHECKV7A-NEXT: movge r0, r12
; CHECKV7A-NEXT: bx lr
br i1 %c, label %then, label %else
then:
Expand Down Expand Up @@ -227,19 +227,19 @@ define i32 @icmp32_sge_0(i32 %x, i32 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV7M-NEXT: lsls r3, r3, #31
; CHECKV7M-NEXT: beq .LBB2_2
; CHECKV7M-NEXT: @ %bb.1: @ %then
; CHECKV7M-NEXT: cmp.w r1, #-1
; CHECKV7M-NEXT: cmp r1, #0
; CHECKV7M-NEXT: mov r1, r12
; CHECKV7M-NEXT: it gt
; CHECKV7M-NEXT: movgt r1, r2
; CHECKV7M-NEXT: cmp.w r0, #-1
; CHECKV7M-NEXT: it gt
; CHECKV7M-NEXT: movgt r12, r2
; CHECKV7M-NEXT: it ge
; CHECKV7M-NEXT: movge r1, r2
; CHECKV7M-NEXT: cmp r0, #0
; CHECKV7M-NEXT: it ge
; CHECKV7M-NEXT: movge r12, r2
; CHECKV7M-NEXT: add.w r0, r12, r1
; CHECKV7M-NEXT: bx lr
; CHECKV7M-NEXT: .LBB2_2: @ %else
; CHECKV7M-NEXT: cmp.w r0, #-1
; CHECKV7M-NEXT: it gt
; CHECKV7M-NEXT: movgt r12, r2
; CHECKV7M-NEXT: cmp r0, #0
; CHECKV7M-NEXT: it ge
; CHECKV7M-NEXT: movge r12, r2
; CHECKV7M-NEXT: mov r0, r12
; CHECKV7M-NEXT: bx lr
;
Expand All @@ -250,19 +250,19 @@ define i32 @icmp32_sge_0(i32 %x, i32 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV7A-NEXT: lsls r3, r3, #31
; CHECKV7A-NEXT: beq .LBB2_2
; CHECKV7A-NEXT: @ %bb.1: @ %then
; CHECKV7A-NEXT: cmp.w r1, #-1
; CHECKV7A-NEXT: cmp r1, #0
; CHECKV7A-NEXT: mov r1, r12
; CHECKV7A-NEXT: it gt
; CHECKV7A-NEXT: movgt r1, r2
; CHECKV7A-NEXT: cmp.w r0, #-1
; CHECKV7A-NEXT: it gt
; CHECKV7A-NEXT: movgt r12, r2
; CHECKV7A-NEXT: it ge
; CHECKV7A-NEXT: movge r1, r2
; CHECKV7A-NEXT: cmp r0, #0
; CHECKV7A-NEXT: it ge
; CHECKV7A-NEXT: movge r12, r2
; CHECKV7A-NEXT: add.w r0, r12, r1
; CHECKV7A-NEXT: bx lr
; CHECKV7A-NEXT: .LBB2_2: @ %else
; CHECKV7A-NEXT: cmp.w r0, #-1
; CHECKV7A-NEXT: it gt
; CHECKV7A-NEXT: movgt r12, r2
; CHECKV7A-NEXT: cmp r0, #0
; CHECKV7A-NEXT: it ge
; CHECKV7A-NEXT: movge r12, r2
; CHECKV7A-NEXT: mov r0, r12
; CHECKV7A-NEXT: bx lr
br i1 %c, label %then, label %else
Expand Down Expand Up @@ -321,19 +321,19 @@ define i32 @icmp32_sgt_m1(i32 %x, i32 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV7M-NEXT: lsls r3, r3, #31
; CHECKV7M-NEXT: beq .LBB3_2
; CHECKV7M-NEXT: @ %bb.1: @ %then
; CHECKV7M-NEXT: cmp.w r1, #-1
; CHECKV7M-NEXT: cmp r1, #0
; CHECKV7M-NEXT: mov r1, r12
; CHECKV7M-NEXT: it gt
; CHECKV7M-NEXT: movgt r1, r2
; CHECKV7M-NEXT: cmp.w r0, #-1
; CHECKV7M-NEXT: it gt
; CHECKV7M-NEXT: movgt r12, r2
; CHECKV7M-NEXT: it ge
; CHECKV7M-NEXT: movge r1, r2
; CHECKV7M-NEXT: cmp r0, #0
; CHECKV7M-NEXT: it ge
; CHECKV7M-NEXT: movge r12, r2
; CHECKV7M-NEXT: add.w r0, r12, r1
; CHECKV7M-NEXT: bx lr
; CHECKV7M-NEXT: .LBB3_2: @ %else
; CHECKV7M-NEXT: cmp.w r1, #-1
; CHECKV7M-NEXT: it gt
; CHECKV7M-NEXT: movgt r12, r2
; CHECKV7M-NEXT: cmp r1, #0
; CHECKV7M-NEXT: it ge
; CHECKV7M-NEXT: movge r12, r2
; CHECKV7M-NEXT: mov r0, r12
; CHECKV7M-NEXT: bx lr
;
Expand All @@ -344,19 +344,19 @@ define i32 @icmp32_sgt_m1(i32 %x, i32 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV7A-NEXT: lsls r3, r3, #31
; CHECKV7A-NEXT: beq .LBB3_2
; CHECKV7A-NEXT: @ %bb.1: @ %then
; CHECKV7A-NEXT: cmp.w r1, #-1
; CHECKV7A-NEXT: cmp r1, #0
; CHECKV7A-NEXT: mov r1, r12
; CHECKV7A-NEXT: it gt
; CHECKV7A-NEXT: movgt r1, r2
; CHECKV7A-NEXT: cmp.w r0, #-1
; CHECKV7A-NEXT: it gt
; CHECKV7A-NEXT: movgt r12, r2
; CHECKV7A-NEXT: it ge
; CHECKV7A-NEXT: movge r1, r2
; CHECKV7A-NEXT: cmp r0, #0
; CHECKV7A-NEXT: it ge
; CHECKV7A-NEXT: movge r12, r2
; CHECKV7A-NEXT: add.w r0, r12, r1
; CHECKV7A-NEXT: bx lr
; CHECKV7A-NEXT: .LBB3_2: @ %else
; CHECKV7A-NEXT: cmp.w r1, #-1
; CHECKV7A-NEXT: it gt
; CHECKV7A-NEXT: movgt r12, r2
; CHECKV7A-NEXT: cmp r1, #0
; CHECKV7A-NEXT: it ge
; CHECKV7A-NEXT: movge r12, r2
; CHECKV7A-NEXT: mov r0, r12
; CHECKV7A-NEXT: bx lr
br i1 %c, label %then, label %else
Expand Down
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