Skip to content

[ARM] Allow FP reg conversion when copying Sx to Dx #147559

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 1 commit into
base: main
Choose a base branch
from
+20 −0
Open

[ARM] Allow FP reg conversion when copying Sx to Dx #147559

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 3 additions & 0 deletions llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -743,6 +743,9 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
Opc = ARM::VMOVSR;
else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.hasFP64())
Opc = ARM::VMOVD;
else if (ARM::DPRRegClass.contains(DestReg) &&
ARM::SPRRegClass.contains(SrcReg) && Subtarget.hasFP64())
Opc = ARM::VCVTDS;
else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
Opc = Subtarget.hasNEON() ? ARM::VORRq : ARM::MQPRCopy;

Expand Down
17 changes: 17 additions & 0 deletions llvm/test/CodeGen/ARM/copy-reg-vcvt.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,17 @@
; RUN: llc -filetype=asm -O3 %s -o - | FileCheck %s
; CHECK: vldr s0, [r0]
; CHECK-NEXT: vcvt.f64.f32 d1, s0

target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv8a-unknown-linux-gnueabihf"

@a = local_unnamed_addr global float 0.000000e+00, align 4

; Function Attrs: mustprogress noimplicitfloat nounwind
define void @_Z1bv() local_unnamed_addr {
entry:
%0 = load float, ptr @a, align 4
tail call void asm sideeffect "", "{d1}"(float %0)
ret void
}

Loading