[LoongArch] Optimize inserting bitcasted integer element or bitcasting extracted fp element

[zhaoqi5]

No description provided.

[llvmbot]

@llvm/pr-subscribers-backend-loongarch

Author: ZhaoQi (zhaoqi5)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/147043.diff

4 Files Affected:

• (modified) llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td (+4-1)
• (modified) llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td (+4-1)
• (modified) llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-bitcast-element.ll (-4)
• (modified) llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-bitcast-element.ll (-4)

diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
index ff7b0f2ae3f25..66476606bb3f8 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
@@ -1593,7 +1593,10 @@ def : Pat<(vector_insert v8i32:$xd, GRLenVT:$rj, uimm3:$imm),
           (XVINSGR2VR_W v8i32:$xd, GRLenVT:$rj, uimm3:$imm)>;
 def : Pat<(vector_insert v4i64:$xd, GRLenVT:$rj, uimm2:$imm),
           (XVINSGR2VR_D v4i64:$xd, GRLenVT:$rj, uimm2:$imm)>;
-
+def : Pat<(vector_insert v8f32:$vd, (loongarch_movgr2fr_w_la64 GPR:$rj), uimm3:$imm),
+          (XVINSGR2VR_W $vd, $rj, uimm3:$imm)>;
+def : Pat<(vector_insert v4f64:$vd, (f64 (bitconvert i64:$rj)), uimm2:$imm),
+          (XVINSGR2VR_D $vd, $rj, uimm2:$imm)>;
 def : Pat<(vector_insert v8f32:$vd, FPR32:$fj, uimm3:$imm),
           (XVINSGR2VR_W $vd, (COPY_TO_REGCLASS FPR32:$fj, GPR), uimm3:$imm)>;
 def : Pat<(vector_insert v4f64:$vd, FPR64:$fj, uimm2:$imm),
diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
index d73d78083ddcd..7bbe6fc972aaf 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
@@ -1791,7 +1791,10 @@ def : Pat<(vector_insert v4i32:$vd, GRLenVT:$rj, uimm2:$imm),
           (VINSGR2VR_W v4i32:$vd, GRLenVT:$rj, uimm2:$imm)>;
 def : Pat<(vector_insert v2i64:$vd, GRLenVT:$rj, uimm1:$imm),
           (VINSGR2VR_D v2i64:$vd, GRLenVT:$rj, uimm1:$imm)>;
-
+def : Pat<(vector_insert v4f32:$vd, (loongarch_movgr2fr_w_la64 GPR:$rj), uimm2:$imm),
+          (VINSGR2VR_W $vd, $rj, uimm2:$imm)>;
+def : Pat<(vector_insert v2f64:$vd, (f64 (bitconvert i64:$rj)), uimm1:$imm),
+          (VINSGR2VR_D $vd, $rj, uimm1:$imm)>;
 def : Pat<(vector_insert v4f32:$vd, FPR32:$fj, uimm2:$imm),
           (VINSGR2VR_W $vd, (COPY_TO_REGCLASS FPR32:$fj, GPR), uimm2:$imm)>;
 def : Pat<(vector_insert v2f64:$vd, FPR64:$fj, uimm1:$imm),
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-bitcast-element.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-bitcast-element.ll
index 7b2461b11f12d..b37b525981fd9 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-bitcast-element.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-bitcast-element.ll
@@ -4,8 +4,6 @@
 define <8 x float> @insert_bitcast_v8f32(<8 x float> %a, i32 %b) nounwind {
 ; CHECK-LABEL: insert_bitcast_v8f32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movgr2fr.w $fa1, $a0
-; CHECK-NEXT:    movfr2gr.s $a0, $fa1
 ; CHECK-NEXT:    xvinsgr2vr.w $xr0, $a0, 1
 ; CHECK-NEXT:    ret
 entry:
@@ -17,8 +15,6 @@ entry:
 define <4 x double> @insert_bitcast_v4f64(<4 x double> %a, i64 %b) nounwind {
 ; CHECK-LABEL: insert_bitcast_v4f64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movgr2fr.d $fa1, $a0
-; CHECK-NEXT:    movfr2gr.d $a0, $fa1
 ; CHECK-NEXT:    xvinsgr2vr.d $xr0, $a0, 1
 ; CHECK-NEXT:    ret
 entry:
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-bitcast-element.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-bitcast-element.ll
index a20d17efdfb11..c42e3013c1131 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-bitcast-element.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-bitcast-element.ll
@@ -4,8 +4,6 @@
 define <4 x float> @insert_bitcast_v4f32(<4 x float> %a, i32 %b) nounwind {
 ; CHECK-LABEL: insert_bitcast_v4f32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movgr2fr.w $fa1, $a0
-; CHECK-NEXT:    movfr2gr.s $a0, $fa1
 ; CHECK-NEXT:    vinsgr2vr.w $vr0, $a0, 1
 ; CHECK-NEXT:    ret
 entry:
@@ -17,8 +15,6 @@ entry:
 define <2 x double> @insert_bitcast_v2f64(<2 x double> %a, i64 %b) nounwind {
 ; CHECK-LABEL: insert_bitcast_v2f64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movgr2fr.d $fa1, $a0
-; CHECK-NEXT:    movfr2gr.d $a0, $fa1
 ; CHECK-NEXT:    vinsgr2vr.d $vr0, $a0, 1
 ; CHECK-NEXT:    ret
 entry:

[SixWeining]

Does this changes also apply to la32?

[zhaoqi5]

Does this changes also apply to la32?

Now la32 occurs error even without this commit. Shows below:

insert_bitcast_v4f64:                   # @insert_bitcast_v4f64
# %bb.0:                                # %entry
	movgr2fr.w	$fa1, $a0
	movgr2frh.w	$fa1, $a1
LLVM ERROR: Attempting to emit MOVFR2GR_D instruction but the Feature_IsLA64 predicate(s) are not met

Seems that vector_insert generates a MOVFR2GR_D which is not legal in la32.

Maybe we should modifiy it and deal with more related to i64 type for la32 in the future.