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[CodeGen] For ad hoc aliasing, additional regUnits are needed to fix lanemask representation #139206

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[CodeGen] For ad hoc aliasing, additional regUnits are needed to fix lanemask representation #139206

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[CodeGen] For ad hoc aliasing, now each lead node register will have
vg0204 May 9, 2025
d8ef3ab
Adding regUnit for leaf registers having aliases only once.
vg0204 May 9, 2025
e804082
Added tableGen test cases, alongwith modified implementation to deal …
vg0204 May 12, 2025
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36 changes: 28 additions & 8 deletions llvm/utils/TableGen/Common/CodeGenRegisters.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -424,20 +424,33 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
// These units correspond to the maximal cliques in the register overlap
// graph which is optimal.
//
// When there is ad hoc aliasing, we simply create one unit per edge in the
// undirected ad hoc aliasing graph. Technically, we could do better by
// identifying maximal cliques in the ad hoc graph, but cliques larger than 2
// are extremely rare anyway (I've never seen one), so we don't bother with
// the added complexity.
// When there is ad hoc aliasing, while we create one unit per edge in the
// undirected ad hoc aliasing graph to represent aliasing, one unit per each
// node leaf register is needed extra to identify them uniquely, in case these
// aliasing register are used as subregister(with disjoint lanemasks) to have
// an accurate lanemask generation for these leaf register.
// For example, In VE, SX0 is made out of disjoint subregister SW0 & SF0
// respectively, where SF0 is an alias for SW0. So while 2 register units will
// uniquely define these 2 subregister, the shared register unit will account
// for aliasing.
//
// Technically, we could do better by identifying maximal cliques in the ad
// hoc graph, but cliques larger than 2 are extremely rare anyway (I've never
// seen one), so we don't bother with the added complexity.
for (CodeGenRegister *AR : ExplicitAliases) {
// Only visit each edge once.
if (AR->SubRegsComplete)
continue;
// Create a RegUnit representing this alias edge, and add it to both
// registers.
unsigned Unit = RegBank.newRegUnit(this, AR);
RegUnits.set(Unit);
AR->RegUnits.set(Unit);
unsigned SharedUnit = RegBank.newRegUnit(this, AR);
RegUnits.set(SharedUnit);
AR->RegUnits.set(SharedUnit);

// Create a RegUnit that now corresponds uniquely to each of the both
// alias leaf register nodes.
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This is assuming that a register that has aliases is also a leaf, i.e. it has no sburegs. I am not sure whether that is a valid assumption.

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@vg0204 vg0204 May 9, 2025 •
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This is assuming that a register that has aliases is also a leaf, i.e. it has no sburegs. I am not sure whether that is a valid assumption.

It should not have subregs at this point, as the register units are created corresponding only to leaf registers, while other regs (including aliases) inherit the regunits of their corresponding subregs. If you see few lines above this changes you would observe.

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I am asking whether any target defines a register with both Aliases and SubRegs. Currently I don't think any in-tree target does that, but it seems like it should be possible (and maybe out-of-tree targets do it?). For example, if the VE register SW0 had subregs for its upper and lower 16 bit halves.

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@vg0204 vg0204 May 12, 2025 •
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I am asking whether any target defines a register with both Aliases and SubRegs.

Yeah, that might need some investigation Or I can add the test for that as suggested by you, that will make things clear. Yeah as you said the current implementation does not apparently seems to handle it, Better to look at it seaparately, can be tracked via added test?

RegUnits.set(RegBank.newRegUnit(this));
AR->RegUnits.set(RegBank.newRegUnit(AR));
}

// Finally, create units for leaf registers without ad hoc aliases. Note that
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As an alternative implementation, could you simply move this block before the "Absent any ad hoc aliasing..." block?

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Why so? Because the handling of leaf register without ad hoc aliasing is really happening after this from line 456 if you see!

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The current logic is:

  1. Inherit regunits from subregs.
  2. Add a regunit for each alias.
  3. If we have no regunits after #⁠1 and #⁠2, it must be a leaf without aliases. Give it a new unique regunit.

I am suggesting swapping #⁠2 and #⁠3:

  1. Inherit regunits from subregs.
  2. If we have no regunits after #⁠1, it must be a leaf. Give it a new unique regunit.
  3. Add a regunit for each alias.

I think this gives the desired behavior.

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@vg0204 vg0204 May 12, 2025 •
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I am suggesting swapping #⁠2 and #⁠3:

This won't do as suppose intially once sw0 got regunit SW0 & SW0-SF0 (after step 2 and 3), at the same time in its step2, sf0 will get its regunit SW0-SF0. So when it comes to register sf0, its step2 (only if regunit empty) to give its unique regunit SW0.

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I see, but it is pretty easy to fix that problem. See #139526

Expand Down Expand Up @@ -2675,6 +2688,13 @@ void CodeGenRegBank::printRegUnitNames(ArrayRef<unsigned> Units) const {
dbgs() << ' ' << RegUnits[Unit].Roots[0]->getName();
else
dbgs() << " #" << Unit;

if (RegUnits[Unit].Roots[1]) {
if (Unit < NumNativeRegUnits)
dbgs() << '~' << RegUnits[Unit].Roots[1]->getName();
else
dbgs() << "~#" << Unit;
}
}
dbgs() << '\n';
}