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[MC] Use StringTable for MCSchedClassDesc names #137012

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236ea03
[MC] Use StringTable for MCSchedClassDesc names
jayfoad Apr 23, 2025
0c4b9d2
Move name table into MCSubtargetInfo
jayfoad Apr 24, 2025
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12 changes: 11 additions & 1 deletion llvm/include/llvm/MC/MCSchedule.h
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Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,7 @@
#define LLVM_MC_MCSCHEDULE_H

#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringTable.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/ErrorHandling.h"
#include <cassert>
Expand Down Expand Up @@ -123,7 +124,7 @@ struct MCSchedClassDesc {
static const unsigned short VariantNumMicroOps = InvalidNumMicroOps - 1;

#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
const char* Name;
unsigned NameOffset;
#endif
uint16_t NumMicroOps : 13;
uint16_t BeginGroup : 1;
Expand Down Expand Up @@ -321,6 +322,9 @@ struct MCSchedModel {
unsigned ProcID;
const MCProcResourceDesc *ProcResourceTable;
const MCSchedClassDesc *SchedClassTable;
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
StringTable SchedClassNameTable = "";
#endif
unsigned NumProcResourceKinds;
unsigned NumSchedClasses;
// Instruction itinerary tables used by InstrItineraryData.
Expand Down Expand Up @@ -408,6 +412,12 @@ struct MCSchedModel {

/// Returns the default initialized model.
static const MCSchedModel Default;

#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
StringRef getSchedClassName(const MCSchedClassDesc *SCDesc) const {
return SchedClassNameTable[SCDesc->NameOffset];
}
#endif
};

// The first three are only template'd arguments so we can get away with leaving
Expand Down
37 changes: 19 additions & 18 deletions llvm/lib/MC/MCSchedule.cpp
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Expand Up @@ -20,24 +20,25 @@

using namespace llvm;

static_assert(std::is_trivial_v<MCSchedModel>,
"MCSchedModel is required to be a trivial type");
const MCSchedModel MCSchedModel::Default = {DefaultIssueWidth,
DefaultMicroOpBufferSize,
DefaultLoopMicroOpBufferSize,
DefaultLoadLatency,
DefaultHighLatency,
DefaultMispredictPenalty,
false,
true,
/*EnableIntervals=*/false,
0,
nullptr,
nullptr,
0,
0,
nullptr,
nullptr};
constexpr MCSchedModel MCSchedModel::Default = {DefaultIssueWidth,
DefaultMicroOpBufferSize,
DefaultLoopMicroOpBufferSize,
DefaultLoadLatency,
DefaultHighLatency,
DefaultMispredictPenalty,
false,
true,
/*EnableIntervals=*/false,
0,
nullptr,
nullptr,
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
"",
#endif
0,
0,
nullptr,
nullptr};

int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI,
const MCSchedClassDesc &SCDesc) {
Expand Down
5 changes: 3 additions & 2 deletions llvm/lib/MCA/InstrBuilder.cpp
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Expand Up @@ -75,8 +75,9 @@ static void initializeUsedResources(InstrDesc &ID,
WithColor::warning()
<< "Ignoring invalid write of zero cycles on processor resource "
<< PR.Name << "\n";
WithColor::note() << "found in scheduling class " << SCDesc.Name
<< " (write index #" << I << ")\n";
WithColor::note() << "found in scheduling class "
<< SM.getSchedClassName(&SCDesc) << " (write index #"
<< I << ")\n";
#endif
continue;
}
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/TableGen/CompressWriteLatencyEntry.td
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Expand Up @@ -33,10 +33,10 @@ def Read_D : SchedRead;
// CHECK-NEXT: }; // MyTargetReadAdvanceTable

// CHECK: static const llvm::MCSchedClassDesc SchedModel_ASchedClasses[] = {
// CHECK-NEXT: {DBGFIELD("InvalidSchedClass") 8191, false, false, false, 0, 0, 0, 0, 0, 0},
// CHECK-NEXT: {DBGFIELD("Inst_A") 1, false, false, false, 0, 0, 1, 1, 0, 0}, // #1
// CHECK-NEXT: {DBGFIELD("Inst_B") 1, false, false, false, 0, 0, 2, 1, 0, 0}, // #2
// CHECK-NEXT: {DBGFIELD("Inst_C") 1, false, false, false, 0, 0, 1, 1, 1, 1}, // #3
// CHECK-NEXT: {DBGFIELD(1 /* InvalidSchedClass */) 8191, false, false, false, 0, 0, 0, 0, 0, 0},
// CHECK-NEXT: {DBGFIELD(19 /* Inst_A */) 1, false, false, false, 0, 0, 1, 1, 0, 0}, // #1
// CHECK-NEXT: {DBGFIELD(26 /* Inst_B */) 1, false, false, false, 0, 0, 2, 1, 0, 0}, // #2
// CHECK-NEXT: {DBGFIELD(33 /* Inst_C */) 1, false, false, false, 0, 0, 1, 1, 1, 1}, // #3
// CHECK-NEXT: }; // SchedModel_ASchedClasses

let SchedModel = SchedModel_A in {
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/TableGen/InvalidMCSchedClassDesc.td
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Expand Up @@ -18,25 +18,25 @@ let CompleteModel = 0 in {

// Inst_B didn't have the resoures, and it is invalid.
// CHECK: SchedModel_ASchedClasses[] = {
// CHECK: {DBGFIELD("Inst_A") 1
// CHECK-NEXT: {DBGFIELD("Inst_B") 8191
// CHECK: {DBGFIELD(19 /* Inst_A */) 1
// CHECK-NEXT: {DBGFIELD(26 /* Inst_B */) 8191
let SchedModel = SchedModel_A in {
def Write_A : SchedWriteRes<[]>;
def : InstRW<[Write_A], (instrs Inst_A)>;
}

// Inst_A didn't have the resoures, and it is invalid.
// CHECK: SchedModel_BSchedClasses[] = {
// CHECK: {DBGFIELD("Inst_A") 8191
// CHECK-NEXT: {DBGFIELD("Inst_B") 1
// CHECK: {DBGFIELD(19 /* Inst_A */) 8191
// CHECK-NEXT: {DBGFIELD(26 /* Inst_B */) 1
let SchedModel = SchedModel_B in {
def Write_B: SchedWriteRes<[]>;
def : InstRW<[Write_B], (instrs Inst_B)>;
}

// CHECK: SchedModel_CSchedClasses[] = {
// CHECK: {DBGFIELD("Inst_A") 1
// CHECK-NEXT: {DBGFIELD("Inst_B") 1
// CHECK: {DBGFIELD(19 /* Inst_A */) 1
// CHECK-NEXT: {DBGFIELD(26 /* Inst_B */) 1
let SchedModel = SchedModel_C in {
def Write_C: SchedWriteRes<[]>;
def : InstRW<[Write_C], (instrs Inst_A, Inst_B)>;
Expand Down
10 changes: 6 additions & 4 deletions llvm/tools/llvm-exegesis/lib/Analysis.cpp
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Expand Up @@ -137,9 +137,9 @@ void Analysis::printInstructionRowCsv(const size_t PointId,
std::tie(SchedClassId, std::ignore) = ResolvedSchedClass::resolveSchedClassId(
State_.getSubtargetInfo(), State_.getInstrInfo(), MCI);
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
const MCSchedClassDesc *const SCDesc =
State_.getSubtargetInfo().getSchedModel().getSchedClassDesc(SchedClassId);
writeEscaped<kEscapeCsv>(OS, SCDesc->Name);
const MCSchedModel &SM = State_.getSubtargetInfo().getSchedModel();
const MCSchedClassDesc *const SCDesc = SM.getSchedClassDesc(SchedClassId);
writeEscaped<kEscapeCsv>(OS, SM.getSchedClassName(SCDesc));
#else
OS << SchedClassId;
#endif
Expand Down Expand Up @@ -563,7 +563,9 @@ Error Analysis::run<Analysis::PrintSchedClassInconsistencies>(
OS << "<div class=\"inconsistency\"><p>Sched Class <span "
"class=\"sched-class-name\">";
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
writeEscaped<kEscapeHtml>(OS, RSCAndPoints.RSC.SCDesc->Name);
const auto &SM = SI.getSchedModel();
writeEscaped<kEscapeHtml>(OS,
SM.getSchedClassName(RSCAndPoints.RSC.SCDesc));
#else
OS << RSCAndPoints.RSC.SchedClassId;
#endif
Expand Down
17 changes: 12 additions & 5 deletions llvm/utils/TableGen/SubtargetEmitter.cpp
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Expand Up @@ -29,6 +29,7 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/StringToOffsetTable.h"
#include "llvm/TableGen/TableGenBackend.h"
#include "llvm/TargetParser/SubtargetFeature.h"
#include <algorithm>
Expand Down Expand Up @@ -1430,6 +1431,7 @@ void SubtargetEmitter::emitSchedClassTables(SchedClassTables &SchedTables,
OS << "}; // " << Target << "ReadAdvanceTable\n";

// Emit a SchedClass table for each processor.
StringToOffsetTable NameTable;
for (const auto &[Idx, Proc] : enumerate(SchedModels.procModels())) {
if (!Proc.hasInstrSchedModel())
continue;
Expand All @@ -1446,14 +1448,17 @@ void SubtargetEmitter::emitSchedClassTables(SchedClassTables &SchedTables,
// name and position.
assert(SchedModels.getSchedClass(0).Name == "NoInstrModel" &&
"invalid class not first");
OS << " {DBGFIELD(\"InvalidSchedClass\") "
unsigned NameOffset = NameTable.GetOrAddStringOffset("InvalidSchedClass");
OS << " {DBGFIELD(" << NameOffset << " /* InvalidSchedClass */) "
<< MCSchedClassDesc::InvalidNumMicroOps
<< ", false, false, false, 0, 0, 0, 0, 0, 0},\n";

for (unsigned SCIdx = 1, SCEnd = SCTab.size(); SCIdx != SCEnd; ++SCIdx) {
MCSchedClassDesc &MCDesc = SCTab[SCIdx];
const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx);
OS << " {DBGFIELD(\"" << SchedClass.Name << "\") ";
NameOffset = NameTable.GetOrAddStringOffset(SchedClass.Name);
OS << " {DBGFIELD(" << NameOffset << " /* " << SchedClass.Name
<< " */) ";
if (SchedClass.Name.size() < 18)
OS.indent(18 - SchedClass.Name.size());
OS << MCDesc.NumMicroOps << ", " << (MCDesc.BeginGroup ? "true" : "false")
Expand All @@ -1467,6 +1472,7 @@ void SubtargetEmitter::emitSchedClassTables(SchedClassTables &SchedTables,
<< MCDesc.NumReadAdvanceEntries << "}, // #" << SCIdx << '\n';
}
OS << "}; // " << Proc.ModelName << "SchedClasses\n";
NameTable.EmitStringTableDef(OS, Proc.ModelName + "SchedClassNames");
}
}

Expand Down Expand Up @@ -1516,10 +1522,11 @@ void SubtargetEmitter::emitProcessorModels(raw_ostream &OS) {
if (PM.hasInstrSchedModel())
OS << " " << PM.ModelName << "ProcResources" << ",\n"
<< " " << PM.ModelName << "SchedClasses" << ",\n"
<< " DBGFIELD(" << PM.ModelName << "SchedClassNames" << ")\n"
<< " " << PM.ProcResourceDefs.size() + 1 << ",\n"
<< " " << SchedModels.schedClasses().size() << ",\n";
else
OS << " nullptr, nullptr, 0, 0,"
OS << " nullptr, nullptr, DBGFIELD(\"\") 0, 0,"
<< " // No instruction-level machine model.\n";
if (PM.hasItineraries())
OS << " " << PM.ItinsDef->getName() << ",\n";
Expand Down Expand Up @@ -1561,10 +1568,10 @@ void SubtargetEmitter::emitSchedModel(raw_ostream &OS) {
}
emitSchedClassTables(SchedTables, OS);

OS << "\n#undef DBGFIELD\n";

// Emit the processor machine model
emitProcessorModels(OS);

OS << "\n#undef DBGFIELD\n";
}

static void emitPredicateProlog(const RecordKeeper &Records, raw_ostream &OS) {
Expand Down
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