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[RISCV] Separate HW/SW shadow stack on RISC-V #112478

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Merged
merged 6 commits into from
Nov 7, 2024
+665 −19
Merged

[RISCV] Separate HW/SW shadow stack on RISC-V #112478

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5a801f6
[RISCV] Separate HW/SW shadow stack on RISC-V
jaidTw Oct 13, 2024
93027ba
[RISCV] Relax the dependency of shadow stack instrs to Zimop
jaidTw Oct 23, 2024
1c2f629
[RISCV] Change the dependency of hw-shadow-stack to Zicfiss
jaidTw Oct 28, 2024
0c6651f
Revert "[RISCV] Relax the dependency of shadow stack instrs to Zimop"
jaidTw Oct 28, 2024
39a8698
!fixup update test
jaidTw Oct 29, 2024
443f392
!fixup rebase and update test
jaidTw Nov 6, 2024
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20 changes: 14 additions & 6 deletions llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -67,10 +67,14 @@ static const std::pair<MCPhysReg, int8_t> FixedCSRFIMap[] = {
static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL) {
if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack))
const auto &STI = MF.getSubtarget<RISCVSubtarget>();
bool HasHWShadowStack = MF.getFunction().hasFnAttribute("hw-shadow-stack") &&
STI.hasStdExtZicfiss();
bool HasSWShadowStack =
MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack);
if (!HasHWShadowStack && !HasSWShadowStack)
return;

const auto &STI = MF.getSubtarget<RISCVSubtarget>();
const llvm::RISCVRegisterInfo *TRI = STI.getRegisterInfo();
Register RAReg = TRI->getRARegister();

Expand All @@ -82,7 +86,7 @@ static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,
return;

const RISCVInstrInfo *TII = STI.getInstrInfo();
if (!STI.hasForcedSWShadowStack() && STI.hasStdExtZicfiss()) {
if (HasHWShadowStack) {
BuildMI(MBB, MI, DL, TII->get(RISCV::SSPUSH)).addReg(RAReg);
return;
}
Expand Down Expand Up @@ -129,10 +133,14 @@ static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,
static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL) {
if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack))
const auto &STI = MF.getSubtarget<RISCVSubtarget>();
bool HasHWShadowStack = MF.getFunction().hasFnAttribute("hw-shadow-stack") &&
STI.hasStdExtZicfiss();
bool HasSWShadowStack =
MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack);
if (!HasHWShadowStack && !HasSWShadowStack)
return;

const auto &STI = MF.getSubtarget<RISCVSubtarget>();
Register RAReg = STI.getRegisterInfo()->getRARegister();

// See emitSCSPrologue() above.
Expand All @@ -142,7 +150,7 @@ static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB,
return;

const RISCVInstrInfo *TII = STI.getInstrInfo();
if (!STI.hasForcedSWShadowStack() && STI.hasStdExtZicfiss()) {
if (HasHWShadowStack) {
BuildMI(MBB, MI, DL, TII->get(RISCV::SSPOPCHK)).addReg(RAReg);
return;
}
Expand Down
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