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[TargetLowering] Change getOptimalMemOpType and findOptimalMemOpLowering to take LLVM Context

backend:AArch64

backend:AMDGPU

backend:ARM

backend:Hexagon

backend:MIPS

backend:PowerPC

backend:RISC-V

backend:SystemZ

backend:X86

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 147664

#147664 In llvm/llvm-project;

· BoyaoWang430 opened on Jul 9, 2025

RuntimeLibcalls: Avoid adding f80 calls to default set

backend:Hexagon

llvm:ir

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 147658

#147658 In llvm/llvm-project;

· arsenm opened on Jul 9, 2025

RuntimeLibcalls: Avoid adding ppcf128 calls to non-ppc targets

backend:Hexagon

llvm:ir

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 147656

#147656 In llvm/llvm-project;

· arsenm opened on Jul 9, 2025

RISCV: Start moving runtime libcall config to tablegen

backend:Hexagon

llvm:ir

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 147652

#147652 In llvm/llvm-project;

· arsenm opened on Jul 9, 2025

RuntimeLibcalls: Stop using defset for default calls

backend:Hexagon

llvm:ir

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 147651

#147651 In llvm/llvm-project;

· arsenm opened on Jul 9, 2025

Hexagon: Move runtime libcall configuration to tablegen

backend:Hexagon

llvm:ir

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 147482

#147482 In llvm/llvm-project;

· arsenm opened on Jul 8, 2025

DAG: Use fast variants of fast math libcalls

backend:ARM

backend:Hexagon

llvm:codegen

llvm:ir

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

tablegen

Status: Open (in progress).

llvm/llvm-projectnumber 147481

#147481 In llvm/llvm-project;

· arsenm opened on Jul 8, 2025

[Hexagon]Handle truncate of v4i8/v2i16 -> v4i1/v2i1 when Hvx is enabled

backend:Hexagon

Status: Open (in progress).

llvm/llvm-projectnumber 147476

#147476 In llvm/llvm-project;

· pkarveti opened on Jul 8, 2025

Hexagon: Add sincos intrinsic test

backend:Hexagon

Status: Open (in progress).

llvm/llvm-projectnumber 147474

#147474 In llvm/llvm-project;

· arsenm opened on Jul 8, 2025

[Hexagon]Handle bitcast of i32/v2i16/v4i8 -> v32i1 when Hvx is enabled

backend:Hexagon

Status: Open (in progress).

llvm/llvm-projectnumber 147466

#147466 In llvm/llvm-project;

· pkarveti opened on Jul 8, 2025

Use F.hasOptSize() instead of checking optsize directly

backend:ARM

backend:Hexagon

llvm:codegen

llvm:transforms

PGOProfile Guided OptimizationsProfile Guided Optimizations

Status: Open (in progress).

llvm/llvm-projectnumber 147348

#147348 In llvm/llvm-project;

· ellishg opened on Jul 7, 2025

[PHIElimination] Reuse existing COPY in predecessor basic block (Take Two)

backend:AArch64

backend:AMDGPU

backend:ARM

backend:Hexagon

backend:loongarch

backend:PowerPC

backend:SystemZ

backend:X86

debuginfo

llvm:codegen

llvm:globalisel

llvm:regalloc

llvm:transforms

Status: Open (in progress).

llvm/llvm-projectnumber 146806

#146806 In llvm/llvm-project;

· guy-david opened on Jul 3, 2025