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Rename StackID
Change-Id: I7962db144b15cf77e0f5a59ad39ee6ed097c1fc0
1 parent e5c923a commit ec899ac

12 files changed

+39
-38
lines changed

‎llvm/include/llvm/CodeGen/MIRYamlMapping.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -378,7 +378,8 @@ struct ScalarEnumerationTraits<TargetStackID::Value> {
378378
IO.enumCase(ID, "default", TargetStackID::Default);
379379
IO.enumCase(ID, "sgpr-spill", TargetStackID::SGPRSpill);
380380
IO.enumCase(ID, "scalable-vector", TargetStackID::ScalableVector);
381-
IO.enumCase(ID, "scalable-pred-vector", TargetStackID::ScalablePredVector);
381+
IO.enumCase(ID, "scalable-predicate-vector",
382+
TargetStackID::ScalablePredicateVector);
382383
IO.enumCase(ID, "wasm-local", TargetStackID::WasmLocal);
383384
IO.enumCase(ID, "noalloc", TargetStackID::NoAlloc);
384385
}

‎llvm/include/llvm/CodeGen/MachineFrameInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -495,13 +495,13 @@ class MachineFrameInfo {
495495
bool contributesToMaxAlignment(uint8_t StackID) {
496496
return StackID == TargetStackID::Default ||
497497
StackID == TargetStackID::ScalableVector ||
498-
StackID == TargetStackID::ScalablePredVector;
498+
StackID == TargetStackID::ScalablePredicateVector;
499499
}
500500

501501
bool isScalableStackID(int ObjectIdx) const {
502502
uint8_t StackID = getStackID(ObjectIdx);
503503
return StackID == TargetStackID::ScalableVector ||
504-
StackID == TargetStackID::ScalablePredVector;
504+
StackID == TargetStackID::ScalablePredicateVector;
505505
}
506506

507507
/// setObjectAlignment - Change the alignment of the specified stack object.

‎llvm/include/llvm/CodeGen/TargetFrameLowering.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ enum Value {
3232
SGPRSpill = 1,
3333
ScalableVector = 2,
3434
WasmLocal = 3,
35-
ScalablePredVector = 4,
35+
ScalablePredicateVector = 4,
3636
NoAlloc = 255
3737
};
3838
}

‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3618,9 +3618,9 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
36183618
if (RPI.isPaired())
36193619
MFI.setStackID(FrameIdxReg2, TargetStackID::ScalableVector);
36203620
} else if (RPI.Type == RegPairInfo::PPR) {
3621-
MFI.setStackID(FrameIdxReg1, TargetStackID::ScalablePredVector);
3621+
MFI.setStackID(FrameIdxReg1, TargetStackID::ScalablePredicateVector);
36223622
if (RPI.isPaired())
3623-
MFI.setStackID(FrameIdxReg2, TargetStackID::ScalablePredVector);
3623+
MFI.setStackID(FrameIdxReg2, TargetStackID::ScalablePredicateVector);
36243624
}
36253625

36263626
if (X0Scratch != AArch64::NoRegister)

‎llvm/lib/Target/AArch64/AArch64FrameLowering.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -111,7 +111,7 @@ class AArch64FrameLowering : public TargetFrameLowering {
111111
return false;
112112
case TargetStackID::Default:
113113
case TargetStackID::ScalableVector:
114-
case TargetStackID::ScalablePredVector:
114+
case TargetStackID::ScalablePredicateVector:
115115
case TargetStackID::NoAlloc:
116116
return true;
117117
}
@@ -121,7 +121,7 @@ class AArch64FrameLowering : public TargetFrameLowering {
121121
// We don't support putting SVE objects into the pre-allocated local
122122
// frame block at the moment.
123123
return (StackId != TargetStackID::ScalableVector &&
124-
StackId != TargetStackID::ScalablePredVector);
124+
StackId != TargetStackID::ScalablePredicateVector);
125125
}
126126

127127
void

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9153,7 +9153,7 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
91539153
if (isScalable) {
91549154
bool IsPred = VA.getValVT() == MVT::aarch64svcount ||
91559155
VA.getValVT().getVectorElementType() == MVT::i1;
9156-
MFI.setStackID(FI, IsPred ? TargetStackID::ScalablePredVector
9156+
MFI.setStackID(FI, IsPred ? TargetStackID::ScalablePredicateVector
91579157
: TargetStackID::ScalableVector);
91589158
}
91599159

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5485,7 +5485,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
54855485
assert(Subtarget.isSVEorStreamingSVEAvailable() &&
54865486
"Unexpected register store without SVE store instructions");
54875487
Opc = AArch64::STR_PXI;
5488-
StackID = TargetStackID::ScalablePredVector;
5488+
StackID = TargetStackID::ScalablePredicateVector;
54895489
}
54905490
break;
54915491
}
@@ -5500,7 +5500,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
55005500
Opc = AArch64::STRSui;
55015501
else if (AArch64::PPR2RegClass.hasSubClassEq(RC)) {
55025502
Opc = AArch64::STR_PPXI;
5503-
StackID = TargetStackID::ScalablePredVector;
5503+
StackID = TargetStackID::ScalablePredicateVector;
55045504
}
55055505
break;
55065506
case 8:
@@ -5662,7 +5662,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
56625662
if (IsPNR)
56635663
PNRReg = DestReg;
56645664
Opc = AArch64::LDR_PXI;
5665-
StackID = TargetStackID::ScalablePredVector;
5665+
StackID = TargetStackID::ScalablePredicateVector;
56665666
}
56675667
break;
56685668
}
@@ -5677,7 +5677,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
56775677
Opc = AArch64::LDRSui;
56785678
else if (AArch64::PPR2RegClass.hasSubClassEq(RC)) {
56795679
Opc = AArch64::LDR_PPXI;
5680-
StackID = TargetStackID::ScalablePredVector;
5680+
StackID = TargetStackID::ScalablePredicateVector;
56815681
}
56825682
break;
56835683
case 8:

‎llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -164,10 +164,10 @@ stack:
164164
- { id: 1, name: z1.addr, size: 16, alignment: 16, stack-id: scalable-vector,
165165
debug-info-variable: '!31', debug-info-expression: '!DIExpression()',
166166
debug-info-location: '!32' }
167-
- { id: 2, name: p0.addr, size: 2, alignment: 2, stack-id: scalable-pred-vector,
167+
- { id: 2, name: p0.addr, size: 2, alignment: 2, stack-id: scalable-predicate-vector,
168168
debug-info-variable: '!33', debug-info-expression: '!DIExpression()',
169169
debug-info-location: '!34' }
170-
- { id: 3, name: p1.addr, size: 2, alignment: 2, stack-id: scalable-pred-vector,
170+
- { id: 3, name: p1.addr, size: 2, alignment: 2, stack-id: scalable-predicate-vector,
171171
debug-info-variable: '!35', debug-info-expression: '!DIExpression()',
172172
debug-info-location: '!36' }
173173
- { id: 4, name: w0.addr, size: 4, alignment: 4, local-offset: -4, debug-info-variable: '!37',
@@ -181,10 +181,10 @@ stack:
181181
- { id: 7, name: localv1, size: 16, alignment: 16, stack-id: scalable-vector,
182182
debug-info-variable: '!45', debug-info-expression: '!DIExpression()',
183183
debug-info-location: '!46' }
184-
- { id: 8, name: localp0, size: 2, alignment: 2, stack-id: scalable-pred-vector,
184+
- { id: 8, name: localp0, size: 2, alignment: 2, stack-id: scalable-predicate-vector,
185185
debug-info-variable: '!48', debug-info-expression: '!DIExpression()',
186186
debug-info-location: '!49' }
187-
- { id: 9, name: localp1, size: 2, alignment: 2, stack-id: scalable-pred-vector,
187+
- { id: 9, name: localp1, size: 2, alignment: 2, stack-id: scalable-predicate-vector,
188188
debug-info-variable: '!51', debug-info-expression: '!DIExpression()',
189189
debug-info-location: '!52' }
190190
machineFunctionInfo: {}

‎llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -96,8 +96,8 @@ stack:
9696
- { id: 1, size: 8, alignment: 8 }
9797
- { id: 2, size: 16, alignment: 16, stack-id: scalable-vector }
9898
- { id: 3, size: 16, alignment: 16, stack-id: scalable-vector }
99-
- { id: 4, size: 2, alignment: 2, stack-id: scalable-pred-vector }
100-
- { id: 5, size: 2, alignment: 2, stack-id: scalable-pred-vector }
99+
- { id: 4, size: 2, alignment: 2, stack-id: scalable-predicate-vector }
100+
- { id: 5, size: 2, alignment: 2, stack-id: scalable-predicate-vector }
101101
machineFunctionInfo: {}
102102
body: |
103103
bb.0.entry:

‎llvm/test/CodeGen/AArch64/framelayout-sve.mir

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -88,7 +88,7 @@
8888
#
8989
# UNWINDINFO: DW_CFA_def_cfa_offset: +16
9090
# UNWINDINFO-NEXT: DW_CFA_offset: reg29 -16
91-
# UNWINDINFO: DW_CFA_def_cfa_offset: +32
91+
# UNWINDINFO: DW_CFA_def_cfa_offset: +32
9292
# UNWINDINFO: DW_CFA_def_cfa_expression: DW_OP_breg31 +0, DW_OP_consts +32, DW_OP_plus, DW_OP_consts +16, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
9393
# UNWINDINFO: DW_CFA_def_cfa: reg31 +32
9494
# UNWINDINFO: DW_CFA_def_cfa_offset: +16
@@ -166,7 +166,7 @@ body: |
166166
# UNWINDINFO: DW_CFA_offset: reg20 -8
167167
# UNWINDINFO-NEXT: DW_CFA_offset: reg21 -16
168168
# UNWINDINFO-NEXT: DW_CFA_offset: reg29 -32
169-
# UNWINDINFO: DW_CFA_def_cfa_offset: +48
169+
# UNWINDINFO: DW_CFA_def_cfa_offset: +48
170170
# UNWINDINFO: DW_CFA_def_cfa_expression: DW_OP_breg31 +0, DW_OP_consts +48, DW_OP_plus, DW_OP_consts +16, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
171171
#
172172
# UNWINDINFO: DW_CFA_def_cfa: reg31 +48
@@ -918,7 +918,7 @@ body: |
918918
# ASM-NEXT: .cfi_escape 0x10, 0x4d, 0x0a, 0x11, 0x60, 0x22, 0x11, 0x50, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d13 @ cfa - 32 - 48 * VG
919919
# ASM-NEXT: .cfi_escape 0x10, 0x4e, 0x0a, 0x11, 0x60, 0x22, 0x11, 0x48, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d14 @ cfa - 32 - 56 * VG
920920
# ASM-NEXT: .cfi_escape 0x10, 0x4f, 0x0a, 0x11, 0x60, 0x22, 0x11, 0x40, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d15 @ cfa - 32 - 64 * VG
921-
# ASM: .cfi_escape 0x0f, 0x0e, 0x8f, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x90, 0x01, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 64 + 144 * VG
921+
# ASM: .cfi_escape 0x0f, 0x0e, 0x8f, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x90, 0x01, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 64 + 144 * VG
922922
# ASM: .cfi_escape 0x0f, 0x0e, 0x8f, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x98, 0x01, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 64 + 152 * VG
923923
#
924924
# ASM: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x20, 0x22, 0x11, 0x98, 0x01, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 32 + 152 * VG
@@ -1165,19 +1165,19 @@ body: |
11651165
# CHECK: - { id: 2, name: '', type: default, offset: -112, size: 16, alignment: 16,
11661166
# CHECK-NEXT: stack-id: scalable-vector,
11671167
# CHECK: - { id: 3, name: '', type: default, offset: -114, size: 2, alignment: 2,
1168-
# CHECK-NEXT: stack-id: scalable-pred-vector,
1168+
# CHECK-NEXT: stack-id: scalable-predicate-vector,
11691169
# CHECK: - { id: 4, name: '', type: spill-slot, offset: -144, size: 16, alignment: 16,
11701170
# CHECK-NEXT: stack-id: scalable-vector,
11711171
# CHECK: - { id: 5, name: '', type: spill-slot, offset: -146, size: 2, alignment: 2,
1172-
# CHECK-NEXT: stack-id: scalable-pred-vector,
1172+
# CHECK-NEXT: stack-id: scalable-predicate-vector,
11731173
# CHECK: - { id: 6, name: '', type: spill-slot, offset: -16, size: 16, alignment: 16,
11741174
# CHECK-NEXT: stack-id: scalable-vector, callee-saved-register: '$z8',
11751175
# CHECK: - { id: 7, name: '', type: spill-slot, offset: -32, size: 16, alignment: 16,
11761176
# CHECK-NEXT: stack-id: scalable-vector, callee-saved-register: '$z23',
11771177
# CHECK: - { id: 8, name: '', type: spill-slot, offset: -34, size: 2, alignment: 2,
1178-
# CHECK-NEXT: stack-id: scalable-pred-vector, callee-saved-register: '$p4',
1178+
# CHECK-NEXT: stack-id: scalable-predicate-vector, callee-saved-register: '$p4',
11791179
# CHECK: - { id: 9, name: '', type: spill-slot, offset: -36, size: 2, alignment: 2,
1180-
# CHECK-NEXT: stack-id: scalable-pred-vector, callee-saved-register: '$p15',
1180+
# CHECK-NEXT: stack-id: scalable-predicate-vector, callee-saved-register: '$p15',
11811181
# CHECK: - { id: 10, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
11821182
# CHECK-NEXT: stack-id: default, callee-saved-register: '$fp',
11831183
#
@@ -1241,9 +1241,9 @@ stack:
12411241
- { id: 0, type: default, size: 32, alignment: 16, stack-id: scalable-vector }
12421242
- { id: 1, type: default, size: 4, alignment: 2, stack-id: scalable-vector }
12431243
- { id: 2, type: default, size: 16, alignment: 16, stack-id: scalable-vector }
1244-
- { id: 3, type: default, size: 2, alignment: 2, stack-id: scalable-pred-vector }
1244+
- { id: 3, type: default, size: 2, alignment: 2, stack-id: scalable-predicate-vector }
12451245
- { id: 4, type: spill-slot, size: 16, alignment: 16, stack-id: scalable-vector }
1246-
- { id: 5, type: spill-slot, size: 2, alignment: 2, stack-id: scalable-pred-vector }
1246+
- { id: 5, type: spill-slot, size: 2, alignment: 2, stack-id: scalable-predicate-vector }
12471247
body: |
12481248
bb.0.entry:
12491249

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