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[Codegen] Add a separate stack ID for scalable predicates
This splits out "ScalablePredVector" from the "ScalableVector" StackID this is primarily to allow easy differentiation between vectors and predicates (without inspecting instructions). This new stack ID is not used in many places yet, but will be used in a later patch to mark stack slots that are known to contain predicates.
1 parent c3d9f31 commit e5c923a

14 files changed

+66
-52
lines changed

‎llvm/include/llvm/CodeGen/MIRYamlMapping.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -378,6 +378,7 @@ struct ScalarEnumerationTraits<TargetStackID::Value> {
378378
IO.enumCase(ID, "default", TargetStackID::Default);
379379
IO.enumCase(ID, "sgpr-spill", TargetStackID::SGPRSpill);
380380
IO.enumCase(ID, "scalable-vector", TargetStackID::ScalableVector);
381+
IO.enumCase(ID, "scalable-pred-vector", TargetStackID::ScalablePredVector);
381382
IO.enumCase(ID, "wasm-local", TargetStackID::WasmLocal);
382383
IO.enumCase(ID, "noalloc", TargetStackID::NoAlloc);
383384
}

‎llvm/include/llvm/CodeGen/MachineFrameInfo.h

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -494,7 +494,14 @@ class MachineFrameInfo {
494494
/// Should this stack ID be considered in MaxAlignment.
495495
bool contributesToMaxAlignment(uint8_t StackID) {
496496
return StackID == TargetStackID::Default ||
497-
StackID == TargetStackID::ScalableVector;
497+
StackID == TargetStackID::ScalableVector ||
498+
StackID == TargetStackID::ScalablePredVector;
499+
}
500+
501+
bool isScalableStackID(int ObjectIdx) const {
502+
uint8_t StackID = getStackID(ObjectIdx);
503+
return StackID == TargetStackID::ScalableVector ||
504+
StackID == TargetStackID::ScalablePredVector;
498505
}
499506

500507
/// setObjectAlignment - Change the alignment of the specified stack object.

‎llvm/include/llvm/CodeGen/TargetFrameLowering.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@ enum Value {
3232
SGPRSpill = 1,
3333
ScalableVector = 2,
3434
WasmLocal = 3,
35+
ScalablePredVector = 4,
3536
NoAlloc = 255
3637
};
3738
}

‎llvm/lib/CodeGen/StackFrameLayoutAnalysisPass.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ struct StackFrameLayoutAnalysis {
7272
: Slot(Idx), Size(MFI.getObjectSize(Idx)),
7373
Align(MFI.getObjectAlign(Idx).value()), Offset(Offset),
7474
SlotTy(Invalid), Scalable(false) {
75-
Scalable = MFI.getStackID(Idx) == TargetStackID::ScalableVector;
75+
Scalable = MFI.isScalableStackID(Idx);
7676
if (MFI.isSpillSlotObjectIndex(Idx))
7777
SlotTy = SlotType::Spill;
7878
else if (MFI.isFixedObjectIndex(Idx))

‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -675,7 +675,7 @@ void AArch64FrameLowering::emitCalleeSavedGPRLocations(
675675
CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameSetup);
676676
for (const auto &Info : CSI) {
677677
unsigned FrameIdx = Info.getFrameIdx();
678-
if (MFI.getStackID(FrameIdx) == TargetStackID::ScalableVector)
678+
if (MFI.isScalableStackID(FrameIdx))
679679
continue;
680680

681681
assert(!Info.isSpilledToReg() && "Spilling to registers not implemented");
@@ -708,7 +708,7 @@ void AArch64FrameLowering::emitCalleeSavedSVELocations(
708708
CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameSetup);
709709

710710
for (const auto &Info : CSI) {
711-
if (!(MFI.getStackID(Info.getFrameIdx()) == TargetStackID::ScalableVector))
711+
if (!MFI.isScalableStackID(Info.getFrameIdx()))
712712
continue;
713713

714714
// Not all unwinders may know about SVE registers, so assume the lowest
@@ -775,8 +775,7 @@ static void emitCalleeSavedRestores(MachineBasicBlock &MBB,
775775
CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameDestroy);
776776

777777
for (const auto &Info : CSI) {
778-
if (SVE !=
779-
(MFI.getStackID(Info.getFrameIdx()) == TargetStackID::ScalableVector))
778+
if (SVE != MFI.isScalableStackID(Info.getFrameIdx()))
780779
continue;
781780

782781
MCRegister Reg = Info.getReg();
@@ -2812,7 +2811,7 @@ AArch64FrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF,
28122811
const auto *AFI = MF.getInfo<AArch64FunctionInfo>();
28132812
bool FPAfterSVECalleeSaves =
28142813
isTargetWindows(MF) && AFI->getSVECalleeSavedStackSize();
2815-
if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
2814+
if (MFI.isScalableStackID(FI)) {
28162815
if (FPAfterSVECalleeSaves &&
28172816
-ObjectOffset <= (int64_t)AFI->getSVECalleeSavedStackSize())
28182817
return StackOffset::getScalable(ObjectOffset);
@@ -2878,7 +2877,7 @@ StackOffset AArch64FrameLowering::resolveFrameIndexReference(
28782877
const auto &MFI = MF.getFrameInfo();
28792878
int64_t ObjectOffset = MFI.getObjectOffset(FI);
28802879
bool isFixed = MFI.isFixedObjectIndex(FI);
2881-
bool isSVE = MFI.getStackID(FI) == TargetStackID::ScalableVector;
2880+
bool isSVE = MFI.isScalableStackID(FI);
28822881
return resolveFrameOffsetReference(MF, ObjectOffset, isFixed, isSVE, FrameReg,
28832882
PreferFP, ForSimm);
28842883
}
@@ -3614,10 +3613,14 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
36143613
}
36153614
// Update the StackIDs of the SVE stack slots.
36163615
MachineFrameInfo &MFI = MF.getFrameInfo();
3617-
if (RPI.Type == RegPairInfo::ZPR || RPI.Type == RegPairInfo::PPR) {
3616+
if (RPI.Type == RegPairInfo::ZPR) {
36183617
MFI.setStackID(FrameIdxReg1, TargetStackID::ScalableVector);
36193618
if (RPI.isPaired())
36203619
MFI.setStackID(FrameIdxReg2, TargetStackID::ScalableVector);
3620+
} else if (RPI.Type == RegPairInfo::PPR) {
3621+
MFI.setStackID(FrameIdxReg1, TargetStackID::ScalablePredVector);
3622+
if (RPI.isPaired())
3623+
MFI.setStackID(FrameIdxReg2, TargetStackID::ScalablePredVector);
36213624
}
36223625

36233626
if (X0Scratch != AArch64::NoRegister)
@@ -3832,8 +3835,7 @@ void AArch64FrameLowering::determineStackHazardSlot(
38323835
for (auto &MI : MBB) {
38333836
std::optional<int> FI = getLdStFrameID(MI, MFI);
38343837
if (FI && *FI >= 0 && *FI < (int)FrameObjects.size()) {
3835-
if (MFI.getStackID(*FI) == TargetStackID::ScalableVector ||
3836-
AArch64InstrInfo::isFpOrNEON(MI))
3838+
if (MFI.isScalableStackID(*FI) || AArch64InstrInfo::isFpOrNEON(MI))
38373839
FrameObjects[*FI] |= 2;
38383840
else
38393841
FrameObjects[*FI] |= 1;
@@ -4301,7 +4303,7 @@ static int64_t determineSVEStackObjectOffsets(MachineFrameInfo &MFI,
43014303
#ifndef NDEBUG
43024304
// First process all fixed stack objects.
43034305
for (int I = MFI.getObjectIndexBegin(); I != 0; ++I)
4304-
assert(MFI.getStackID(I) != TargetStackID::ScalableVector &&
4306+
assert(!MFI.isScalableStackID(I) &&
43054307
"SVE vectors should never be passed on the stack by value, only by "
43064308
"reference.");
43074309
#endif
@@ -4335,12 +4337,11 @@ static int64_t determineSVEStackObjectOffsets(MachineFrameInfo &MFI,
43354337
int StackProtectorFI = -1;
43364338
if (MFI.hasStackProtectorIndex()) {
43374339
StackProtectorFI = MFI.getStackProtectorIndex();
4338-
if (MFI.getStackID(StackProtectorFI) == TargetStackID::ScalableVector)
4340+
if (MFI.isScalableStackID(StackProtectorFI))
43394341
ObjectsToAllocate.push_back(StackProtectorFI);
43404342
}
43414343
for (int I = 0, E = MFI.getObjectIndexEnd(); I != E; ++I) {
4342-
unsigned StackID = MFI.getStackID(I);
4343-
if (StackID != TargetStackID::ScalableVector)
4344+
if (!MFI.isScalableStackID(I))
43444345
continue;
43454346
if (I == StackProtectorFI)
43464347
continue;
@@ -5372,8 +5373,7 @@ void AArch64FrameLowering::orderFrameObjects(
53725373
if (AFI.hasStackHazardSlotIndex()) {
53735374
std::optional<int> FI = getLdStFrameID(MI, MFI);
53745375
if (FI && *FI >= 0 && *FI < (int)FrameObjects.size()) {
5375-
if (MFI.getStackID(*FI) == TargetStackID::ScalableVector ||
5376-
AArch64InstrInfo::isFpOrNEON(MI))
5376+
if (MFI.isScalableStackID(*FI) || AArch64InstrInfo::isFpOrNEON(MI))
53775377
FrameObjects[*FI].Accesses |= FrameObject::AccessFPR;
53785378
else
53795379
FrameObjects[*FI].Accesses |= FrameObject::AccessGPR;
@@ -5731,7 +5731,7 @@ void AArch64FrameLowering::emitRemarks(
57315731
}
57325732

57335733
unsigned RegTy = StackAccess::AccessType::GPR;
5734-
if (MFI.getStackID(FrameIdx) == TargetStackID::ScalableVector) {
5734+
if (MFI.isScalableStackID(FrameIdx)) {
57355735
// SPILL_PPR_TO_ZPR_SLOT_PSEUDO and FILL_PPR_FROM_ZPR_SLOT_PSEUDO
57365736
// spill/fill the predicate as a data vector (so are an FPR access).
57375737
if (MI.getOpcode() != AArch64::SPILL_PPR_TO_ZPR_SLOT_PSEUDO &&

‎llvm/lib/Target/AArch64/AArch64FrameLowering.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -111,6 +111,7 @@ class AArch64FrameLowering : public TargetFrameLowering {
111111
return false;
112112
case TargetStackID::Default:
113113
case TargetStackID::ScalableVector:
114+
case TargetStackID::ScalablePredVector:
114115
case TargetStackID::NoAlloc:
115116
return true;
116117
}
@@ -119,7 +120,8 @@ class AArch64FrameLowering : public TargetFrameLowering {
119120
bool isStackIdSafeForLocalArea(unsigned StackId) const override {
120121
// We don't support putting SVE objects into the pre-allocated local
121122
// frame block at the moment.
122-
return StackId != TargetStackID::ScalableVector;
123+
return (StackId != TargetStackID::ScalableVector &&
124+
StackId != TargetStackID::ScalablePredVector);
123125
}
124126

125127
void

‎llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7487,7 +7487,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
74877487
int FI = cast<FrameIndexSDNode>(N)->getIndex();
74887488
// We can only encode VL scaled offsets, so only fold in frame indexes
74897489
// referencing SVE objects.
7490-
if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
7490+
if (MFI.isScalableStackID(FI)) {
74917491
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
74927492
OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i64);
74937493
return true;
@@ -7533,7 +7533,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
75337533
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
75347534
// We can only encode VL scaled offsets, so only fold in frame indexes
75357535
// referencing SVE objects.
7536-
if (MFI.getStackID(FI) == TargetStackID::ScalableVector)
7536+
if (MFI.isScalableStackID(FI))
75377537
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
75387538
}
75397539

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -8714,8 +8714,7 @@ void AArch64TargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
87148714
(MI.getOpcode() == AArch64::ADDXri ||
87158715
MI.getOpcode() == AArch64::SUBXri)) {
87168716
const MachineOperand &MO = MI.getOperand(1);
8717-
if (MO.isFI() && MF.getFrameInfo().getStackID(MO.getIndex()) ==
8718-
TargetStackID::ScalableVector)
8717+
if (MO.isFI() && MF.getFrameInfo().isScalableStackID(MO.getIndex()))
87198718
MI.addOperand(MachineOperand::CreateReg(AArch64::VG, /*IsDef=*/false,
87208719
/*IsImplicit=*/true));
87218720
}
@@ -9151,8 +9150,12 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
91519150
Align Alignment = DAG.getDataLayout().getPrefTypeAlign(Ty);
91529151
MachineFrameInfo &MFI = MF.getFrameInfo();
91539152
int FI = MFI.CreateStackObject(StoreSize, Alignment, false);
9154-
if (isScalable)
9155-
MFI.setStackID(FI, TargetStackID::ScalableVector);
9153+
if (isScalable) {
9154+
bool IsPred = VA.getValVT() == MVT::aarch64svcount ||
9155+
VA.getValVT().getVectorElementType() == MVT::i1;
9156+
MFI.setStackID(FI, IsPred ? TargetStackID::ScalablePredVector
9157+
: TargetStackID::ScalableVector);
9158+
}
91569159

91579160
MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI);
91589161
SDValue Ptr = DAG.getFrameIndex(
@@ -28554,7 +28557,7 @@ void AArch64TargetLowering::finalizeLowering(MachineFunction &MF) const {
2855428557
// than doing it here in finalizeLowering.
2855528558
if (MFI.hasStackProtectorIndex()) {
2855628559
for (unsigned int i = 0, e = MFI.getObjectIndexEnd(); i != e; ++i) {
28557-
if (MFI.getStackID(i) == TargetStackID::ScalableVector &&
28560+
if (MFI.isScalableStackID(i) &&
2855828561
MFI.getObjectSSPLayout(i) != MachineFrameInfo::SSPLK_None) {
2855928562
MFI.setStackID(MFI.getStackProtectorIndex(),
2856028563
TargetStackID::ScalableVector);

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5485,7 +5485,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
54855485
assert(Subtarget.isSVEorStreamingSVEAvailable() &&
54865486
"Unexpected register store without SVE store instructions");
54875487
Opc = AArch64::STR_PXI;
5488-
StackID = TargetStackID::ScalableVector;
5488+
StackID = TargetStackID::ScalablePredVector;
54895489
}
54905490
break;
54915491
}
@@ -5500,7 +5500,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
55005500
Opc = AArch64::STRSui;
55015501
else if (AArch64::PPR2RegClass.hasSubClassEq(RC)) {
55025502
Opc = AArch64::STR_PPXI;
5503-
StackID = TargetStackID::ScalableVector;
5503+
StackID = TargetStackID::ScalablePredVector;
55045504
}
55055505
break;
55065506
case 8:
@@ -5662,7 +5662,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
56625662
if (IsPNR)
56635663
PNRReg = DestReg;
56645664
Opc = AArch64::LDR_PXI;
5665-
StackID = TargetStackID::ScalableVector;
5665+
StackID = TargetStackID::ScalablePredVector;
56665666
}
56675667
break;
56685668
}
@@ -5677,7 +5677,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
56775677
Opc = AArch64::LDRSui;
56785678
else if (AArch64::PPR2RegClass.hasSubClassEq(RC)) {
56795679
Opc = AArch64::LDR_PPXI;
5680-
StackID = TargetStackID::ScalableVector;
5680+
StackID = TargetStackID::ScalablePredVector;
56815681
}
56825682
break;
56835683
case 8:

‎llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -164,10 +164,10 @@ stack:
164164
- { id: 1, name: z1.addr, size: 16, alignment: 16, stack-id: scalable-vector,
165165
debug-info-variable: '!31', debug-info-expression: '!DIExpression()',
166166
debug-info-location: '!32' }
167-
- { id: 2, name: p0.addr, size: 2, alignment: 2, stack-id: scalable-vector,
167+
- { id: 2, name: p0.addr, size: 2, alignment: 2, stack-id: scalable-pred-vector,
168168
debug-info-variable: '!33', debug-info-expression: '!DIExpression()',
169169
debug-info-location: '!34' }
170-
- { id: 3, name: p1.addr, size: 2, alignment: 2, stack-id: scalable-vector,
170+
- { id: 3, name: p1.addr, size: 2, alignment: 2, stack-id: scalable-pred-vector,
171171
debug-info-variable: '!35', debug-info-expression: '!DIExpression()',
172172
debug-info-location: '!36' }
173173
- { id: 4, name: w0.addr, size: 4, alignment: 4, local-offset: -4, debug-info-variable: '!37',
@@ -181,10 +181,10 @@ stack:
181181
- { id: 7, name: localv1, size: 16, alignment: 16, stack-id: scalable-vector,
182182
debug-info-variable: '!45', debug-info-expression: '!DIExpression()',
183183
debug-info-location: '!46' }
184-
- { id: 8, name: localp0, size: 2, alignment: 2, stack-id: scalable-vector,
184+
- { id: 8, name: localp0, size: 2, alignment: 2, stack-id: scalable-pred-vector,
185185
debug-info-variable: '!48', debug-info-expression: '!DIExpression()',
186186
debug-info-location: '!49' }
187-
- { id: 9, name: localp1, size: 2, alignment: 2, stack-id: scalable-vector,
187+
- { id: 9, name: localp1, size: 2, alignment: 2, stack-id: scalable-pred-vector,
188188
debug-info-variable: '!51', debug-info-expression: '!DIExpression()',
189189
debug-info-location: '!52' }
190190
machineFunctionInfo: {}

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