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PPCMCCodeEmitter: Set PCRel at fixup creation
Avoid reliance on the MCAssembler::evaluateFixup workaround that checks MCFixupKindInfo::FKF_IsPCRel. Additionally, standardize how fixups are appended. This helper will facilitate future fixup data structure optimizations.
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+40
-37
lines changed

2 files changed

+40
-37
lines changed

‎llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -149,30 +149,32 @@ class PPCAsmBackend : public MCAsmBackend {
149149
} // end anonymous namespace
150150

151151
MCFixupKindInfo PPCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
152+
// clang-format off
152153
const static MCFixupKindInfo InfosBE[PPC::NumTargetFixupKinds] = {
153154
// name offset bits flags
154-
{"fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel},
155-
{"fixup_ppc_br24_notoc", 6, 24, MCFixupKindInfo::FKF_IsPCRel},
156-
{"fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel},
155+
{"fixup_ppc_br24", 6, 24, 0},
156+
{"fixup_ppc_br24_notoc", 6, 24, 0},
157+
{"fixup_ppc_brcond14", 16, 14, 0},
157158
{"fixup_ppc_br24abs", 6, 24, 0},
158159
{"fixup_ppc_brcond14abs", 16, 14, 0},
159160
{"fixup_ppc_half16", 0, 16, 0},
160161
{"fixup_ppc_half16ds", 0, 14, 0},
161-
{"fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel},
162+
{"fixup_ppc_pcrel34", 0, 34, 0},
162163
{"fixup_ppc_imm34", 0, 34, 0},
163164
{"fixup_ppc_nofixup", 0, 0, 0}};
164165
const static MCFixupKindInfo InfosLE[PPC::NumTargetFixupKinds] = {
165166
// name offset bits flags
166-
{"fixup_ppc_br24", 2, 24, MCFixupKindInfo::FKF_IsPCRel},
167-
{"fixup_ppc_br24_notoc", 2, 24, MCFixupKindInfo::FKF_IsPCRel},
168-
{"fixup_ppc_brcond14", 2, 14, MCFixupKindInfo::FKF_IsPCRel},
167+
{"fixup_ppc_br24", 2, 24, 0},
168+
{"fixup_ppc_br24_notoc", 2, 24, 0},
169+
{"fixup_ppc_brcond14", 2, 14, 0},
169170
{"fixup_ppc_br24abs", 2, 24, 0},
170171
{"fixup_ppc_brcond14abs", 2, 14, 0},
171172
{"fixup_ppc_half16", 0, 16, 0},
172173
{"fixup_ppc_half16ds", 2, 14, 0},
173-
{"fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel},
174+
{"fixup_ppc_pcrel34", 0, 34, 0},
174175
{"fixup_ppc_imm34", 0, 34, 0},
175176
{"fixup_ppc_nofixup", 0, 0, 0}};
177+
// clang-format on
176178

177179
// Fixup kinds from .reloc directive are like R_PPC_NONE/R_PPC64_NONE. They
178180
// do not require any extra processing.

‎llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp

Lines changed: 30 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,19 @@ MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
3939
return new PPCMCCodeEmitter(MCII, Ctx);
4040
}
4141

42+
static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
43+
const MCExpr *Value, uint16_t Kind) {
44+
bool PCRel = false;
45+
switch (Kind) {
46+
case PPC::fixup_ppc_br24:
47+
case PPC::fixup_ppc_br24_notoc:
48+
case PPC::fixup_ppc_brcond14:
49+
case PPC::fixup_ppc_pcrel34:
50+
PCRel = true;
51+
}
52+
Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel));
53+
}
54+
4255
unsigned PPCMCCodeEmitter::
4356
getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
4457
SmallVectorImpl<MCFixup> &Fixups,
@@ -49,10 +62,9 @@ getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
4962
return getMachineOpValue(MI, MO, Fixups, STI);
5063

5164
// Add a fixup for the branch target.
52-
Fixups.push_back(MCFixup::create(0, MO.getExpr(),
53-
(isNoTOCCallInstr(MI)
54-
? (MCFixupKind)PPC::fixup_ppc_br24_notoc
55-
: (MCFixupKind)PPC::fixup_ppc_br24)));
65+
addFixup(
66+
Fixups, 0, MO.getExpr(),
67+
(isNoTOCCallInstr(MI) ? PPC::fixup_ppc_br24_notoc : PPC::fixup_ppc_br24));
5668
return 0;
5769
}
5870

@@ -157,8 +169,7 @@ unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
157169
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
158170

159171
// Add a fixup for the branch target.
160-
Fixups.push_back(MCFixup::create(0, MO.getExpr(),
161-
(MCFixupKind)PPC::fixup_ppc_brcond14));
172+
addFixup(Fixups, 0, MO.getExpr(), PPC::fixup_ppc_brcond14);
162173
return 0;
163174
}
164175

@@ -170,8 +181,7 @@ getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
170181
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
171182

172183
// Add a fixup for the branch target.
173-
Fixups.push_back(MCFixup::create(0, MO.getExpr(),
174-
(MCFixupKind)PPC::fixup_ppc_br24abs));
184+
addFixup(Fixups, 0, MO.getExpr(), PPC::fixup_ppc_br24abs);
175185
return 0;
176186
}
177187

@@ -183,8 +193,7 @@ getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
183193
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
184194

185195
// Add a fixup for the branch target.
186-
Fixups.push_back(MCFixup::create(0, MO.getExpr(),
187-
(MCFixupKind)PPC::fixup_ppc_brcond14abs));
196+
addFixup(Fixups, 0, MO.getExpr(), PPC::fixup_ppc_brcond14abs);
188197
return 0;
189198
}
190199

@@ -205,8 +214,7 @@ unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
205214
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
206215

207216
// Add a fixup for the immediate field.
208-
Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
209-
(MCFixupKind)PPC::fixup_ppc_half16));
217+
addFixup(Fixups, IsLittleEndian ? 0 : 2, MO.getExpr(), PPC::fixup_ppc_half16);
210218
return 0;
211219
}
212220

@@ -220,7 +228,7 @@ uint64_t PPCMCCodeEmitter::getImm34Encoding(const MCInst &MI, unsigned OpNo,
220228
return getMachineOpValue(MI, MO, Fixups, STI);
221229

222230
// Add a fixup for the immediate field.
223-
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Fixup));
231+
addFixup(Fixups, 0, MO.getExpr(), Fixup);
224232
return 0;
225233
}
226234

@@ -248,8 +256,7 @@ unsigned PPCMCCodeEmitter::getDispRIEncoding(const MCInst &MI, unsigned OpNo,
248256
return getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF;
249257

250258
// Add a fixup for the displacement field.
251-
Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
252-
(MCFixupKind)PPC::fixup_ppc_half16));
259+
addFixup(Fixups, IsLittleEndian ? 0 : 2, MO.getExpr(), PPC::fixup_ppc_half16);
253260
return 0;
254261
}
255262

@@ -262,8 +269,8 @@ PPCMCCodeEmitter::getDispRIXEncoding(const MCInst &MI, unsigned OpNo,
262269
return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF);
263270

264271
// Add a fixup for the displacement field.
265-
Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
266-
(MCFixupKind)PPC::fixup_ppc_half16ds));
272+
addFixup(Fixups, IsLittleEndian ? 0 : 2, MO.getExpr(),
273+
PPC::fixup_ppc_half16ds);
267274
return 0;
268275
}
269276

@@ -279,8 +286,8 @@ PPCMCCodeEmitter::getDispRIX16Encoding(const MCInst &MI, unsigned OpNo,
279286
}
280287

281288
// Otherwise add a fixup for the displacement field.
282-
Fixups.push_back(MCFixup::create(IsLittleEndian ? 0 : 2, MO.getExpr(),
283-
(MCFixupKind)PPC::fixup_ppc_half16dq));
289+
addFixup(Fixups, IsLittleEndian ? 0 : 2, MO.getExpr(),
290+
PPC::fixup_ppc_half16dq);
284291
return 0;
285292
}
286293

@@ -335,9 +342,7 @@ PPCMCCodeEmitter::getDispRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
335342
"specifier must be S_PCREL, S_GOT_PCREL, S_GOT_TLSGD_PCREL, "
336343
"S_GOT_TLSLD_PCREL, or S_GOT_TPREL_PCREL");
337344
// Generate the fixup for the relocation.
338-
Fixups.push_back(
339-
MCFixup::create(0, Expr,
340-
static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
345+
addFixup(Fixups, 0, Expr, PPC::fixup_ppc_pcrel34);
341346
// Put zero in the location of the immediate. The linker will fill in the
342347
// correct value based on the relocation.
343348
return 0;
@@ -369,9 +374,7 @@ PPCMCCodeEmitter::getDispRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
369374
getSpecifier(SRE) == PPC::S_GOT_PCREL) &&
370375
"VariantKind must be VK_PCREL or VK_GOT_PCREL");
371376
// Generate the fixup for the relocation.
372-
Fixups.push_back(
373-
MCFixup::create(0, Expr,
374-
static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
377+
addFixup(Fixups, 0, Expr, PPC::fixup_ppc_pcrel34);
375378
// Put zero in the location of the immediate. The linker will fill in the
376379
// correct value based on the relocation.
377380
return 0;
@@ -431,8 +434,7 @@ unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
431434
const MCExpr *Expr = MO.getExpr();
432435
const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr);
433436
bool IsPCRel = getSpecifier(SRE) == PPC::S_TLS_PCREL;
434-
Fixups.push_back(MCFixup::create(IsPCRel ? 1 : 0, Expr,
435-
(MCFixupKind)PPC::fixup_ppc_nofixup));
437+
addFixup(Fixups, IsPCRel ? 1 : 0, Expr, PPC::fixup_ppc_nofixup);
436438
const Triple &TT = STI.getTargetTriple();
437439
bool isPPC64 = TT.isPPC64();
438440
return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
@@ -445,8 +447,7 @@ unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
445447
// (__tls_get_addr), which we create via getDirectBrEncoding as usual,
446448
// and one for the TLSGD or TLSLD symbol, which is emitted here.
447449
const MCOperand &MO = MI.getOperand(OpNo+1);
448-
Fixups.push_back(MCFixup::create(0, MO.getExpr(),
449-
(MCFixupKind)PPC::fixup_ppc_nofixup));
450+
addFixup(Fixups, 0, MO.getExpr(), PPC::fixup_ppc_nofixup);
450451
return getDirectBrEncoding(MI, OpNo, Fixups, STI);
451452
}
452453

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