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ARMMCCodeEmitter: Set PCRel at fixup creation
Avoid reliance on the MCAssembler::evaluateFixup workaround that checks MCFixupKindInfo::FKF_IsPCRel. Additionally, standardize how fixups are appended. This helper will facilitate future fixup data structure optimizations.
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2 files changed

+147
-119
lines changed

2 files changed

+147
-119
lines changed

‎llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

Lines changed: 60 additions & 78 deletions
Original file line numberDiff line numberDiff line change
@@ -70,44 +70,34 @@ MCFixupKindInfo ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
7070
// ARMFixupKinds.h.
7171
//
7272
// Name Offset (bits) Size (bits) Flags
73-
{"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
73+
{"fixup_arm_ldst_pcrel_12", 0, 32, 0},
7474
{"fixup_t2_ldst_pcrel_12", 0, 32,
75-
MCFixupKindInfo::FKF_IsPCRel |
76-
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
77-
{"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
78-
{"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
79-
{"fixup_t2_pcrel_10", 0, 32,
80-
MCFixupKindInfo::FKF_IsPCRel |
81-
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
82-
{"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
83-
{"fixup_t2_pcrel_9", 0, 32,
84-
MCFixupKindInfo::FKF_IsPCRel |
85-
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
75+
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
76+
{"fixup_arm_pcrel_10_unscaled", 0, 32, 0},
77+
{"fixup_arm_pcrel_10", 0, 32, 0},
78+
{"fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
79+
{"fixup_arm_pcrel_9", 0, 32, 0},
80+
{"fixup_t2_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
8681
{"fixup_arm_ldst_abs_12", 0, 32, 0},
8782
{"fixup_thumb_adr_pcrel_10", 0, 8,
88-
MCFixupKindInfo::FKF_IsPCRel |
89-
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
90-
{"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
83+
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
84+
{"fixup_arm_adr_pcrel_12", 0, 32, 0},
9185
{"fixup_t2_adr_pcrel_12", 0, 32,
92-
MCFixupKindInfo::FKF_IsPCRel |
93-
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
94-
{"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
95-
{"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
96-
{"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
97-
{"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
98-
{"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
99-
{"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
100-
{"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
101-
{"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
102-
{"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
86+
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
87+
{"fixup_arm_condbranch", 0, 24, 0},
88+
{"fixup_arm_uncondbranch", 0, 24, 0},
89+
{"fixup_t2_condbranch", 0, 32, 0},
90+
{"fixup_t2_uncondbranch", 0, 32, 0},
91+
{"fixup_arm_thumb_br", 0, 16, 0},
92+
{"fixup_arm_uncondbl", 0, 24, 0},
93+
{"fixup_arm_condbl", 0, 24, 0},
94+
{"fixup_arm_blx", 0, 24, 0},
95+
{"fixup_arm_thumb_bl", 0, 32, 0},
10396
{"fixup_arm_thumb_blx", 0, 32,
104-
MCFixupKindInfo::FKF_IsPCRel |
105-
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
106-
{"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
107-
{"fixup_arm_thumb_cp", 0, 8,
108-
MCFixupKindInfo::FKF_IsPCRel |
109-
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
110-
{"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel},
97+
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
98+
{"fixup_arm_thumb_cb", 0, 16, 0},
99+
{"fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
100+
{"fixup_arm_thumb_bcc", 0, 8, 0},
111101
// movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
112102
// - 19.
113103
{"fixup_arm_movt_hi16", 0, 20, 0},
@@ -120,56 +110,47 @@ MCFixupKindInfo ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
120110
{"fixup_arm_thumb_lower_0_7", 0, 8, 0},
121111
{"fixup_arm_mod_imm", 0, 12, 0},
122112
{"fixup_t2_so_imm", 0, 26, 0},
123-
{"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
124-
{"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
125-
{"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
126-
{"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
113+
{"fixup_bf_branch", 0, 32, 0},
114+
{"fixup_bf_target", 0, 32, 0},
115+
{"fixup_bfl_target", 0, 32, 0},
116+
{"fixup_bfc_target", 0, 32, 0},
127117
{"fixup_bfcsel_else_target", 0, 32, 0},
128-
{"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
129-
{"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}};
118+
{"fixup_wls", 0, 32, 0},
119+
{"fixup_le", 0, 32, 0},
120+
};
130121
const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
131122
// This table *must* be in the order that the fixup_* kinds are defined in
132123
// ARMFixupKinds.h.
133124
//
134125
// Name Offset (bits) Size (bits) Flags
135-
{"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
126+
{"fixup_arm_ldst_pcrel_12", 0, 32, 0},
136127
{"fixup_t2_ldst_pcrel_12", 0, 32,
137-
MCFixupKindInfo::FKF_IsPCRel |
138-
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
139-
{"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
140-
{"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
141-
{"fixup_t2_pcrel_10", 0, 32,
142-
MCFixupKindInfo::FKF_IsPCRel |
143-
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
144-
{"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
145-
{"fixup_t2_pcrel_9", 0, 32,
146-
MCFixupKindInfo::FKF_IsPCRel |
147-
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
128+
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
129+
{"fixup_arm_pcrel_10_unscaled", 0, 32, 0},
130+
{"fixup_arm_pcrel_10", 0, 32, 0},
131+
{"fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
132+
{"fixup_arm_pcrel_9", 0, 32, 0},
133+
{"fixup_t2_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
148134
{"fixup_arm_ldst_abs_12", 0, 32, 0},
149135
{"fixup_thumb_adr_pcrel_10", 8, 8,
150-
MCFixupKindInfo::FKF_IsPCRel |
151-
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
152-
{"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
136+
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
137+
{"fixup_arm_adr_pcrel_12", 0, 32, 0},
153138
{"fixup_t2_adr_pcrel_12", 0, 32,
154-
MCFixupKindInfo::FKF_IsPCRel |
155-
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
156-
{"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
157-
{"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
158-
{"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
159-
{"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
160-
{"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
161-
{"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
162-
{"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
163-
{"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
164-
{"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
139+
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
140+
{"fixup_arm_condbranch", 8, 24, 0},
141+
{"fixup_arm_uncondbranch", 8, 24, 0},
142+
{"fixup_t2_condbranch", 0, 32, 0},
143+
{"fixup_t2_uncondbranch", 0, 32, 0},
144+
{"fixup_arm_thumb_br", 0, 16, 0},
145+
{"fixup_arm_uncondbl", 8, 24, 0},
146+
{"fixup_arm_condbl", 8, 24, 0},
147+
{"fixup_arm_blx", 8, 24, 0},
148+
{"fixup_arm_thumb_bl", 0, 32, 0},
165149
{"fixup_arm_thumb_blx", 0, 32,
166-
MCFixupKindInfo::FKF_IsPCRel |
167-
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
168-
{"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
169-
{"fixup_arm_thumb_cp", 8, 8,
170-
MCFixupKindInfo::FKF_IsPCRel |
171-
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
172-
{"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel},
150+
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
151+
{"fixup_arm_thumb_cb", 0, 16, 0},
152+
{"fixup_arm_thumb_cp", 8, 8, MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
153+
{"fixup_arm_thumb_bcc", 8, 8, 0},
173154
// movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
174155
// - 19.
175156
{"fixup_arm_movt_hi16", 12, 20, 0},
@@ -182,13 +163,14 @@ MCFixupKindInfo ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
182163
{"fixup_arm_thumb_lower_0_7", 24, 8, 0},
183164
{"fixup_arm_mod_imm", 20, 12, 0},
184165
{"fixup_t2_so_imm", 26, 6, 0},
185-
{"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
186-
{"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
187-
{"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
188-
{"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
166+
{"fixup_bf_branch", 0, 32, 0},
167+
{"fixup_bf_target", 0, 32, 0},
168+
{"fixup_bfl_target", 0, 32, 0},
169+
{"fixup_bfc_target", 0, 32, 0},
189170
{"fixup_bfcsel_else_target", 0, 32, 0},
190-
{"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
191-
{"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}};
171+
{"fixup_wls", 0, 32, 0},
172+
{"fixup_le", 0, 32, 0},
173+
};
192174

193175
// Fixup kinds from .reloc directive are like R_ARM_NONE. They do not require
194176
// any extra processing.

‎llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

Lines changed: 87 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -313,41 +313,12 @@ class ARMMCCodeEmitter : public MCCodeEmitter {
313313

314314
unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
315315
SmallVectorImpl<MCFixup> &Fixups,
316-
const MCSubtargetInfo &ST) const {
317-
const MCOperand &MO = MI.getOperand(Op);
318-
319-
// Support for fixups (MCFixup)
320-
if (MO.isExpr()) {
321-
const MCExpr *Expr = MO.getExpr();
322-
// Fixups resolve to plain values that need to be encoded.
323-
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_mod_imm);
324-
Fixups.push_back(MCFixup::create(0, Expr, Kind));
325-
return 0;
326-
}
327-
328-
// Immediate is already in its encoded format
329-
return MO.getImm();
330-
}
316+
const MCSubtargetInfo &ST) const;
331317

332318
/// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
333319
unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
334-
SmallVectorImpl<MCFixup> &Fixups,
335-
const MCSubtargetInfo &STI) const {
336-
const MCOperand &MO = MI.getOperand(Op);
337-
338-
// Support for fixups (MCFixup)
339-
if (MO.isExpr()) {
340-
const MCExpr *Expr = MO.getExpr();
341-
// Fixups resolve to plain values that need to be encoded.
342-
MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_so_imm);
343-
Fixups.push_back(MCFixup::create(0, Expr, Kind));
344-
return 0;
345-
}
346-
unsigned SoImm = MO.getImm();
347-
unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
348-
assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
349-
return Encoded;
350-
}
320+
SmallVectorImpl<MCFixup> &Fixups,
321+
const MCSubtargetInfo &STI) const;
351322

352323
unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
353324
SmallVectorImpl<MCFixup> &Fixups,
@@ -462,6 +433,44 @@ class ARMMCCodeEmitter : public MCCodeEmitter {
462433

463434
} // end anonymous namespace
464435

436+
static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
437+
const MCExpr *Value, uint16_t Kind) {
438+
bool PCRel = false;
439+
switch (Kind) {
440+
case ARM::fixup_arm_ldst_pcrel_12:
441+
case ARM::fixup_t2_ldst_pcrel_12:
442+
case ARM::fixup_arm_pcrel_10_unscaled:
443+
case ARM::fixup_arm_pcrel_10:
444+
case ARM::fixup_t2_pcrel_10:
445+
case ARM::fixup_arm_pcrel_9:
446+
case ARM::fixup_t2_pcrel_9:
447+
case ARM::fixup_thumb_adr_pcrel_10:
448+
case ARM::fixup_arm_adr_pcrel_12:
449+
case ARM::fixup_t2_adr_pcrel_12:
450+
case ARM::fixup_arm_condbranch:
451+
case ARM::fixup_arm_uncondbranch:
452+
case ARM::fixup_t2_condbranch:
453+
case ARM::fixup_t2_uncondbranch:
454+
case ARM::fixup_arm_thumb_br:
455+
case ARM::fixup_arm_uncondbl:
456+
case ARM::fixup_arm_condbl:
457+
case ARM::fixup_arm_blx:
458+
case ARM::fixup_arm_thumb_bl:
459+
case ARM::fixup_arm_thumb_blx:
460+
case ARM::fixup_arm_thumb_cb:
461+
case ARM::fixup_arm_thumb_cp:
462+
case ARM::fixup_arm_thumb_bcc:
463+
case ARM::fixup_bf_branch:
464+
case ARM::fixup_bf_target:
465+
case ARM::fixup_bfl_target:
466+
case ARM::fixup_bfc_target:
467+
case ARM::fixup_wls:
468+
case ARM::fixup_le:
469+
PCRel = true;
470+
}
471+
Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel));
472+
}
473+
465474
/// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
466475
/// instructions, and rewrite them to their Thumb2 form if we are currently in
467476
/// Thumb2 mode.
@@ -616,7 +625,7 @@ static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
616625
assert(MO.isExpr() && "Unexpected branch target type!");
617626
const MCExpr *Expr = MO.getExpr();
618627
MCFixupKind Kind = MCFixupKind(FixupKind);
619-
Fixups.push_back(MCFixup::create(0, Expr, Kind));
628+
addFixup(Fixups, 0, Expr, Kind);
620629

621630
// All of the information is in the fixup.
622631
return 0;
@@ -979,7 +988,7 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
979988
Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
980989
isAdd = false; // 'U' bit is set as part of the fixup.
981990
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_ldst_abs_12);
982-
Fixups.push_back(MCFixup::create(0, MO1.getExpr(), Kind));
991+
addFixup(Fixups, 0, MO1.getExpr(), Kind);
983992
}
984993
} else if (MO.isExpr()) {
985994
Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
@@ -989,7 +998,7 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
989998
Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
990999
else
9911000
Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
992-
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
1001+
addFixup(Fixups, 0, MO.getExpr(), Kind);
9931002

9941003
++MCNumCPRelocations;
9951004
} else {
@@ -1114,7 +1123,7 @@ getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
11141123
assert(MO.isExpr() && "Unexpected machine operand type!");
11151124
const MCExpr *Expr = MO.getExpr();
11161125
MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1117-
Fixups.push_back(MCFixup::create(0, Expr, Kind));
1126+
addFixup(Fixups, 0, Expr, Kind);
11181127

11191128
++MCNumCPRelocations;
11201129
} else
@@ -1251,7 +1260,7 @@ uint32_t ARMMCCodeEmitter::getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx,
12511260
break;
12521261
}
12531262

1254-
Fixups.push_back(MCFixup::create(0, E, Kind));
1263+
addFixup(Fixups, 0, E, Kind);
12551264
return 0;
12561265
}
12571266
// If the expression doesn't have :upper16:, :lower16: on it, it's just a
@@ -1373,7 +1382,7 @@ getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
13731382
assert(MO.isExpr() && "Unexpected machine operand type!");
13741383
const MCExpr *Expr = MO.getExpr();
13751384
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1376-
Fixups.push_back(MCFixup::create(0, Expr, Kind));
1385+
addFixup(Fixups, 0, Expr, Kind);
13771386

13781387
++MCNumCPRelocations;
13791388
return (Rn << 9) | (1 << 13);
@@ -1455,7 +1464,7 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
14551464
Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
14561465
else
14571466
Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1458-
Fixups.push_back(MCFixup::create(0, Expr, Kind));
1467+
addFixup(Fixups, 0, Expr, Kind);
14591468

14601469
++MCNumCPRelocations;
14611470
} else {
@@ -1495,7 +1504,7 @@ getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
14951504
Kind = MCFixupKind(ARM::fixup_t2_pcrel_9);
14961505
else
14971506
Kind = MCFixupKind(ARM::fixup_arm_pcrel_9);
1498-
Fixups.push_back(MCFixup::create(0, Expr, Kind));
1507+
addFixup(Fixups, 0, Expr, Kind);
14991508

15001509
++MCNumCPRelocations;
15011510
} else {
@@ -1511,6 +1520,43 @@ getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
15111520
return Binary;
15121521
}
15131522

1523+
unsigned ARMMCCodeEmitter::getModImmOpValue(const MCInst &MI, unsigned Op,
1524+
SmallVectorImpl<MCFixup> &Fixups,
1525+
const MCSubtargetInfo &ST) const {
1526+
const MCOperand &MO = MI.getOperand(Op);
1527+
1528+
// Support for fixups (MCFixup)
1529+
if (MO.isExpr()) {
1530+
const MCExpr *Expr = MO.getExpr();
1531+
// Fixups resolve to plain values that need to be encoded.
1532+
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_mod_imm);
1533+
addFixup(Fixups, 0, Expr, Kind);
1534+
return 0;
1535+
}
1536+
1537+
// Immediate is already in its encoded format
1538+
return MO.getImm();
1539+
}
1540+
1541+
unsigned ARMMCCodeEmitter::getT2SOImmOpValue(const MCInst &MI, unsigned Op,
1542+
SmallVectorImpl<MCFixup> &Fixups,
1543+
const MCSubtargetInfo &STI) const {
1544+
const MCOperand &MO = MI.getOperand(Op);
1545+
1546+
// Support for fixups (MCFixup)
1547+
if (MO.isExpr()) {
1548+
const MCExpr *Expr = MO.getExpr();
1549+
// Fixups resolve to plain values that need to be encoded.
1550+
MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_so_imm);
1551+
addFixup(Fixups, 0, Expr, Kind);
1552+
return 0;
1553+
}
1554+
unsigned SoImm = MO.getImm();
1555+
unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
1556+
assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
1557+
return Encoded;
1558+
}
1559+
15141560
unsigned ARMMCCodeEmitter::
15151561
getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
15161562
SmallVectorImpl<MCFixup> &Fixups,
@@ -1950,7 +1996,7 @@ ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
19501996
const MCExpr *DiffExpr = MCBinaryExpr::createSub(
19511997
MO.getExpr(), BranchMO.getExpr(), CTX);
19521998
MCFixupKind Kind = MCFixupKind(ARM::fixup_bfcsel_else_target);
1953-
Fixups.push_back(llvm::MCFixup::create(0, DiffExpr, Kind));
1999+
addFixup(Fixups, 0, DiffExpr, Kind);
19542000
return 0;
19552001
}
19562002

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