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HexagonMCCodeEmitter: Set PCRel at fixup creation
Avoid reliance on the MCAssembler::evaluateFixup workaround that checks MCFixupKindInfo::FKF_IsPCRel. Additionally, standardize how fixups are appended. This helper will facilitate future fixup data structure optimizations.
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+52
-24
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2 files changed

+52
-24
lines changed

‎llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp

Lines changed: 22 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -84,14 +84,15 @@ class HexagonAsmBackend : public MCAsmBackend {
8484
}
8585

8686
MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override {
87+
// clang-format off
8788
const static MCFixupKindInfo Infos[Hexagon::NumTargetFixupKinds] = {
8889
// This table *must* be in same the order of fixup_* kinds in
8990
// HexagonFixupKinds.h.
9091
//
9192
// namei offset bits flags
92-
{ "fixup_Hexagon_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
93-
{ "fixup_Hexagon_B15_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
94-
{ "fixup_Hexagon_B7_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
93+
{ "fixup_Hexagon_B22_PCREL", 0, 32, 0 },
94+
{ "fixup_Hexagon_B15_PCREL", 0, 32, 0 },
95+
{ "fixup_Hexagon_B7_PCREL", 0, 32, 0 },
9596
{ "fixup_Hexagon_LO16", 0, 32, 0 },
9697
{ "fixup_Hexagon_HI16", 0, 32, 0 },
9798
{ "fixup_Hexagon_32", 0, 32, 0 },
@@ -102,15 +103,15 @@ class HexagonAsmBackend : public MCAsmBackend {
102103
{ "fixup_Hexagon_GPREL16_2", 0, 32, 0 },
103104
{ "fixup_Hexagon_GPREL16_3", 0, 32, 0 },
104105
{ "fixup_Hexagon_HL16", 0, 32, 0 },
105-
{ "fixup_Hexagon_B13_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
106-
{ "fixup_Hexagon_B9_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
107-
{ "fixup_Hexagon_B32_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
106+
{ "fixup_Hexagon_B13_PCREL", 0, 32, 0 },
107+
{ "fixup_Hexagon_B9_PCREL", 0, 32, 0 },
108+
{ "fixup_Hexagon_B32_PCREL_X", 0, 32, 0 },
108109
{ "fixup_Hexagon_32_6_X", 0, 32, 0 },
109-
{ "fixup_Hexagon_B22_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
110-
{ "fixup_Hexagon_B15_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
111-
{ "fixup_Hexagon_B13_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
112-
{ "fixup_Hexagon_B9_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
113-
{ "fixup_Hexagon_B7_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
110+
{ "fixup_Hexagon_B22_PCREL_X", 0, 32, 0 },
111+
{ "fixup_Hexagon_B15_PCREL_X", 0, 32, 0 },
112+
{ "fixup_Hexagon_B13_PCREL_X", 0, 32, 0 },
113+
{ "fixup_Hexagon_B9_PCREL_X", 0, 32, 0 },
114+
{ "fixup_Hexagon_B7_PCREL_X", 0, 32, 0 },
114115
{ "fixup_Hexagon_16_X", 0, 32, 0 },
115116
{ "fixup_Hexagon_12_X", 0, 32, 0 },
116117
{ "fixup_Hexagon_11_X", 0, 32, 0 },
@@ -119,12 +120,12 @@ class HexagonAsmBackend : public MCAsmBackend {
119120
{ "fixup_Hexagon_8_X", 0, 32, 0 },
120121
{ "fixup_Hexagon_7_X", 0, 32, 0 },
121122
{ "fixup_Hexagon_6_X", 0, 32, 0 },
122-
{ "fixup_Hexagon_32_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
123+
{ "fixup_Hexagon_32_PCREL", 0, 32, 0 },
123124
{ "fixup_Hexagon_COPY", 0, 32, 0 },
124125
{ "fixup_Hexagon_GLOB_DAT", 0, 32, 0 },
125126
{ "fixup_Hexagon_JMP_SLOT", 0, 32, 0 },
126127
{ "fixup_Hexagon_RELATIVE", 0, 32, 0 },
127-
{ "fixup_Hexagon_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
128+
{ "fixup_Hexagon_PLT_B22_PCREL", 0, 32, 0 },
128129
{ "fixup_Hexagon_GOTREL_LO16", 0, 32, 0 },
129130
{ "fixup_Hexagon_GOTREL_HI16", 0, 32, 0 },
130131
{ "fixup_Hexagon_GOTREL_32", 0, 32, 0 },
@@ -137,8 +138,8 @@ class HexagonAsmBackend : public MCAsmBackend {
137138
{ "fixup_Hexagon_DTPREL_HI16", 0, 32, 0 },
138139
{ "fixup_Hexagon_DTPREL_32", 0, 32, 0 },
139140
{ "fixup_Hexagon_DTPREL_16", 0, 32, 0 },
140-
{ "fixup_Hexagon_GD_PLT_B22_PCREL",0, 32, MCFixupKindInfo::FKF_IsPCRel },
141-
{ "fixup_Hexagon_LD_PLT_B22_PCREL",0, 32, MCFixupKindInfo::FKF_IsPCRel },
141+
{ "fixup_Hexagon_GD_PLT_B22_PCREL",0, 32, 0 },
142+
{ "fixup_Hexagon_LD_PLT_B22_PCREL",0, 32, 0 },
142143
{ "fixup_Hexagon_GD_GOT_LO16", 0, 32, 0 },
143144
{ "fixup_Hexagon_GD_GOT_HI16", 0, 32, 0 },
144145
{ "fixup_Hexagon_GD_GOT_32", 0, 32, 0 },
@@ -159,7 +160,7 @@ class HexagonAsmBackend : public MCAsmBackend {
159160
{ "fixup_Hexagon_TPREL_HI16", 0, 32, 0 },
160161
{ "fixup_Hexagon_TPREL_32", 0, 32, 0 },
161162
{ "fixup_Hexagon_TPREL_16", 0, 32, 0 },
162-
{ "fixup_Hexagon_6_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
163+
{ "fixup_Hexagon_6_PCREL_X", 0, 32, 0 },
163164
{ "fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0 },
164165
{ "fixup_Hexagon_GOTREL_16_X", 0, 32, 0 },
165166
{ "fixup_Hexagon_GOTREL_11_X", 0, 32, 0 },
@@ -183,11 +184,12 @@ class HexagonAsmBackend : public MCAsmBackend {
183184
{ "fixup_Hexagon_TPREL_32_6_X", 0, 32, 0 },
184185
{ "fixup_Hexagon_TPREL_16_X", 0, 32, 0 },
185186
{ "fixup_Hexagon_TPREL_11_X", 0, 32, 0 },
186-
{ "fixup_Hexagon_GD_PLT_B22_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
187-
{ "fixup_Hexagon_GD_PLT_B32_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
188-
{ "fixup_Hexagon_LD_PLT_B22_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
189-
{ "fixup_Hexagon_LD_PLT_B32_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel }
187+
{ "fixup_Hexagon_GD_PLT_B22_PCREL_X", 0, 32, 0 },
188+
{ "fixup_Hexagon_GD_PLT_B32_PCREL_X", 0, 32, 0 },
189+
{ "fixup_Hexagon_LD_PLT_B22_PCREL_X", 0, 32, 0 },
190+
{ "fixup_Hexagon_LD_PLT_B32_PCREL_X", 0, 32, 0 },
190191
};
192+
// clang-format on
191193

192194
if (Kind < FirstTargetFixupKind)
193195
return MCAsmBackend::getFixupKindInfo(Kind);

‎llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp

Lines changed: 30 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -337,6 +337,35 @@ static const std::map<unsigned, std::vector<unsigned>> StdFixups = {
337337
#undef P
338338
#undef _
339339

340+
static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
341+
const MCExpr *Value, uint16_t Kind) {
342+
bool PCRel = false;
343+
switch (Kind) {
344+
case Hexagon::fixup_Hexagon_B22_PCREL:
345+
case Hexagon::fixup_Hexagon_B15_PCREL:
346+
case Hexagon::fixup_Hexagon_B7_PCREL:
347+
case Hexagon::fixup_Hexagon_B13_PCREL:
348+
case Hexagon::fixup_Hexagon_B9_PCREL:
349+
case Hexagon::fixup_Hexagon_B32_PCREL_X:
350+
case Hexagon::fixup_Hexagon_B22_PCREL_X:
351+
case Hexagon::fixup_Hexagon_B15_PCREL_X:
352+
case Hexagon::fixup_Hexagon_B13_PCREL_X:
353+
case Hexagon::fixup_Hexagon_B9_PCREL_X:
354+
case Hexagon::fixup_Hexagon_B7_PCREL_X:
355+
case Hexagon::fixup_Hexagon_32_PCREL:
356+
case Hexagon::fixup_Hexagon_PLT_B22_PCREL:
357+
case Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL:
358+
case Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL:
359+
case Hexagon::fixup_Hexagon_6_PCREL_X:
360+
case Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL_X:
361+
case Hexagon::fixup_Hexagon_GD_PLT_B32_PCREL_X:
362+
case Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL_X:
363+
case Hexagon::fixup_Hexagon_LD_PLT_B32_PCREL_X:
364+
PCRel = true;
365+
}
366+
Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel));
367+
}
368+
340369
uint32_t HexagonMCCodeEmitter::parseBits(size_t Last, MCInst const &MCB,
341370
MCInst const &MCI) const {
342371
bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI);
@@ -698,10 +727,7 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
698727
FixupExpr = MCBinaryExpr::createAdd(FixupExpr, C, MCT);
699728
}
700729

701-
MCFixup Fixup =
702-
MCFixup::create(State.Addend, FixupExpr, MCFixupKind(FixupKind));
703-
Fixups.push_back(Fixup);
704-
// All of the information is in the fixup.
730+
addFixup(Fixups, State.Addend, FixupExpr, FixupKind);
705731
return 0;
706732
}
707733

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